Software-Compiled System Design defines a C-based design approach to dramatically improve design productivity and quality for embedded systems containing both hardware and software elements. This methodology introduces software flexibility to system design using an iterative Specify -> Design -> Compile flow that provides hardware/software co-design, cycle-accurate functional co-verification, generation of VHDL or Verilog from C-based code, and direct synthesis from C to FPGA hardware.

In this case study, a JPEG2000 algorithm starting from a C language specification is implemented in a Field Programmable System on Chip (FPSoC). Initially, the system functionality is verified and profiled in C-code as software running on an embedded processor. Next, Celoxica co-design capabilities are used to explore the design space and partition the design between embedded software and FPGA logic. Finally, the implementation is optimized through direct hardware synthesis from C-based code. The design results from the JPEG2000 case study are presented to show how this system design methodology improves design performance while significantly reducing design time.