This section offers a brief look at the challenges faced by today’s design engineers, as well as an overview of the topics covered in this seminar.


NOTE: This page provides previews of each session. For full access, register here.

Andrei Vladimirescu of UC Berkeley discusses historical issues relating to the design of ICs, along with a detailed look into the upcoming design challenges as analog content continues to increase.

Functional Verification
This session covers many of the issues relating to the effective simulation of analog/mixed-signal designs. Topics include ideal tools and methodologies for simulating Verilog/VHDL digital circuits, analog-only circuits, analog IP, custom digital/mixed-signal circuits and embedded memories.
Physical Verification and Extraction
Analog/mixed-signal SoCs require robust, design-style independent LVS and parasitic extraction. Tools for physical verification and extraction of SoCs must handle a variety of design styles while maintaining correctness and accuracy. Furthermore, using LVS/PEX must enable the user to achieve accurate simulation results with best-in-class analysis solutions. This session covers physical verification and extraction technologies that are ideally suited for the unique challenges of analog/mixed-signal SoC design.
Design Flow and Chip Assembly
Historically, design creation and capture tools have addressed either a purely analog schematic capture, or exclusively digital design flow. This session explores methods for overcoming the challenges of analog/mixed-signal SoC designs, using a single design assembly tool that supports design data handling of both analog schematic-based- and top down language-based designs.



  Coming soon:
Cadence, Synplicity & Quickturn—seventeen demos in all.