After Gary and I spoke, I went around the DAC floor looking at what either of us had chosen as the Must Sees. Here's
the first 7 inteviews. There are 14 more to follow. Enjoy! - John
EVE vs. Mentor
EVE Zebu and the new Mentor Veloce vs. the Cadence Palladium monopoly. A really fun interview. No holds barred.
CLK Amber™
EDA veteran Isadore Katz returns taking on the PrimeTime monopoly in the static timing analysis game.
Breker Treker™
Some weird "graph based verification" tool that Gary really loved. I sort of understood it. Sort of.
Synopsys DC-Topo
DC-Topo, power opto & estimates, CTS, PhysOpt fading, congestion and what's coming up in rev 2007.12.
Sequence CoolTime™
CoolTime, IR-drop, I/O design, and SSN; plus voltage islands, power gating, RTL and PowerTheater 65.
Bluespec Azur IP™
How Bluespec succeeded in the ESNUG 459 #5 challenge that Forte ducked out on. Brett hates this company.
Altos Variety™
Libs for statistical static timing analysis tools. (Libs for Synopsys, Extreme DA, Cadence, Mentor, and Blaze.
I don't think they have Magma yet.)
Bluespec Technical Overview
The Bluespec toolset, the only ESL synthesis solution for control logic and
complex datapaths, significantly accelerates hardware design and reduces
verification costs. Bluespec presents hardware designers an exciting new way to
implement a design with correct-by-construction control logic synthesis while
retaining full control over the architecture and performance of the design.
This technical overview provides a review of the toolset, examples, technology
and key benefits.
ZeBu: The Fastest Verification
ZeBu is an advanced hardware-assisted verification platform that combines the
best aspects of traditional emulation and rapid prototyping systems into a
single, unified environment for both ASIC/SoC debugging and embedded software
validation. With the high capacity, easy setup and debugging associated with
emulation, and the price/ performance of rapid prototyping, EVE enables both
hardware designers and software developers to collaborate on a common design
representation.
Advanced SystemC Debug with Vista™
Mentor Graphics' Vista™ is the industry's most advanced SystemC debug toolset,
providing powerful hardware and C/C++ oriented views and debugging mechanisms.
Vista dramatically reduces ESL and SystemC debugging cycles and enables
hardware engineers to effectively trace C/C++ constructs within a familiar
hardware debugging platform.
Sequence Design-For-Power Flow
Attack the challenges of low power design holistically, from RTL to GDS. Manage
and reduce power. Avoid power problems. The only comprehensive tool suite, with
advantages for managers, for SoC architects and designers, and for the physical
implementation team: Design for Power with Sequence.
DEMOS ON DEMAND™ on DeepChip
