Accelicon Adveda Apache Design Solutions Apex Design Systems Arithmatica Beach Solutions Bluespec Calypto ChipVision Design Systems CoFluent Eagleware-Elanix GigaScale IC Golden Gate Technology Impulse Accelerated Technology Manhattan Routing Mirabilis Design Orion Consuliting Posedge Software Prolific Silicon Dimensions Spiratech Synfora Tensilica Tharas Systems Z Circuit Automation
     
 
Accelicon Technologies is an EDA company dedicated to provide world-class solutions to analog, RF and mixed signal semiconductor companies. Currently Accelicon provides the industry's first, and leading, solution for Analog Virtual Prototyping (AVP), as well as a number of SPICE model quality assurance (MQA) and model builder program (MBP) products addressing foundry model verification, documentation, and model library version and SPICE platform comparison.
 
MQA (SPICE Model Quality Assurance) Demo
Model Quality Assurance (MQA) automatically assesses the quality of foundry-supplied models, generates the documentation, and compares multiple model libraries, versions, and SPICE platforms. Model Builder Program (MBP) generates and optimizes SPICE models using data from silicon wafer testing.
     
 
AdvEDA helps both HW- and SW- developers to close the SOC verification gap by offering fast and fully integrated simulation and debugging tools. With these tools both the hardware and software of a System-On-Chip can be verified within one environment.
 
Adveda Miss Universe Demo
Miss Univers is a complete HW/SW co-verification tool for multi-processor SOC architectures, offering extensive debug capabilities, fast simulation and emulation support. It includes an RTL simulator as well as a multi-core IDE with most fascinating debug features and configurable user-friendly graphical user interface.
     
 
Apache Design Solutions provides physical design integrity solutions for high performance nanometer SoC designs that focus on power, timing, signal, and system I/O integrity.
 
Dynamic Power Integrity Flow Using RedHawk Demo
Power is one of the top concerns at 130 nanometer processes and below, especially for those used in low power applications. In order to achieve optimal performance and yield for these designs, the integrity of the P/G design must be maintained. This demo shows how Apache's RedHawk and PsiWinder analyze the impact of dynamic voltage drop on critical path timing and automatically fix and optimize P/G "hot spots."
     
 
Apex Design Systems' core competence is design reoptimization. Apex is the industry's leader in physical optimization through space propagation. Space propagation redistributes the space in a chip or module to achieve better routability, area, timing, power and yield. The technology also maintains relative locations of standard cells and can therefore iteratively improve a design to achieve better quality of results.
 
Compex-RT Demo
Compex-RT is a space propagation tool for improving routability and/or achieve die size reduction. This demo will include Compex-RT's usable space analysis, routability analysis, timing analysis, and space propagation for improved routability and die size reduction.
     
 
Arithmatica is a silicon math company that provides solutions for designers of math-critical ICs - those ICs whose specification depends on math performance or where the complexity of math is greater than 250,000 gates. Our solutions are based on fundamental improvements in silicon arithmetic. Our unique IP products provide significant, permanent improvement to licensees' arithmetic IC circuits. Headquarters are in Redwood City, California, and the R&D Center is located in Warwick, England.
 
CellMath™ demo - COMING SOON!
Arithmatica provides Intellectual Property for complex math circuits exceeding 250,000 gates. Our solutions are based on fundamental improvements in silicon arithmetic.
     
 
Beach Solutions aims to establish itself as the recognized world leader in IP packaging, integration and re-use. Our automatic generation technology will allow Beach Solutions to continue to grow profitably by automating the production of new tools to the benefit of its customers in the dynamic System-on-Chip development markets.
 
EASI-Studio™
EASI-Studio is a suite of tools that capture and validate embedded system specifications and automate the creation and reproduction of many of the design files required for successful system development—while seamlessly integrating with existing version control systems.
     
 
Bluespec provides an industry standards-based EDA toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high quality RTL, without compromised speed, power or area. The toolset allows ASIC and FPGA designers to significantly reduce design time, bugs and re-spins that contribute to product delays and escalating costs.
 
Blueview & Novas Debussy Demo
Cycle accurate C-based simulation with full Verilog support provides both speed and debug visibility needed to truly raise the level of design abstraction.
     
 
Calypto Design Systems is a privately held EDA company focused on bridging electronic system-level design and integrated circuit (IC) implementation. Calypto products reduce IC design verification time and costs and increase flexibility and confidence in design and architectural optimization.
 
SLEC™: The Industry’s First Sequential Equivalence Checker
As the industry’s first sequential equivalence checker, SLEC can verify block-level designs with differences in sequential and data abstraction. SLEC provides comprehensive functional verification for designers doing micro-architectural RTL optimization, such as re-timing, pipelining, and resource sharing, and engineering teams deploying system-level design flows including those using behavioral synthesis.
     
 
ChipVision Design Systems is the leading supplier of low power analysis, estimation and optimization solutions to design teams of System on Chips (SoCs). ChipVision’s power estimation and optimization offering ORINOCO is the only design tool that bridges the Electronic System Level (ESL), at which the most significant reduction of power consumption can be achieved, to low power implementation at the RT Level. Target application areas are power-sensitive electronic devices in the wireless and multimedia domain.
 
ChipVision ORINOCO®
This in-depth demo shows how ORINOCO enables you to define the low-power optimized micro architecture for data-flow dominated blocks in SoCs. Starting from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro architecture of a block for implementation and guides your optimization of the number of algorithmic resources, memory accesses and allocations, resulting in the best low-power architecture.
     
 
Cofluent Design's mission is to provide intuitive system-level hardware/software co-design tools and methodology that enable developers of embedded systems and systems-on-chip to create, verify and optimize designs that meet customer's requirements at lower costs.
 
 
CoFluent Studio™
This in-depth demo shows how CoFluent Studio enables electronic system developers to define the right architecture for the right functionality early in their projects. First, developers model and simulate the system’s real-time application with its time properties in a hardware/software-agnostic way from simple graphics and C/C++ code entry. Next, they simulate at high abstraction level the execution of the application and inter-processor communications on different models of hardware platforms to obtain prospective performance figures. Last, developers generate the C code for implementing the software tasks of the application model on a RTOS.
     
 
Eagleware-Elanix offers SystemView by Elanix, the Windows®-based design tool for system-level modeling of mixed signal communications, distortion true RF/Analog, and bit-true DSP systems. Applications include satellite communication, wireless and wired communication, Optics, 3G, CDMA, DVB, Bluetooth, 802.11x, UWB, RF/Analog, S-Parameters, DSP, ANSII C-code generation, and much more.
 
 
SystemView by Elanix
SystemView by Elanix is used to design, model and simulate a complete BER analysis of a QPSK system with encoded pulse shaped signals — and to evaluate system performance by tuning components (such as filters and RF amplifiers) to fit design specifications.
     
 
GigaScale IC is an electronic design automation (EDA) pioneer developing the first specification optimization system for integrated circuit (IC) design.
 
InCyte®
InCyte® is a revolutionary new specification optimization system that dramatically reduces the risk, design time and cost of IC design. It accurately estimates key IC specifications including; size, power, leakage, speed, cost, and yield.
     
 
Golden Gate Technology's mission is to be the gold standard in power reduction products for IC designers who are facing daunting power system design and power consumption issues. Golden Gate Tech's solutions, Power Optimize Gold™ and Power Plan Gold™, enhance existing design flows from major EDA vendors to optimize and minimize both leakage and switching power while simultaneously meeting constraints for timing, signal integrity, electromigration, and design for manufacturability.
 
Power Plan Gold™ and Power Optimize Gold™
Power Plan Gold (PPG) efficiently creates complex power grids with unique Parametric Templates™ technology, PPG natively supports multiple supplies, analyzes the power grid for IR drop and EM violations and automatically repairs the grid. Power Optimize Gold automatically reduces power consumption by 15 – 20% or more using a proprietary WiresFirst™ algorithm while maintaining timing, SI, and EM constraints.
     
 
Impulse Accelerated Technology provides compiler tools allowing embedded systems designers to compile ANSI C code to mixed hardware/software programmable targets including FPGAs and FPGA-based programmable platforms. Impulse products include CoDeveloper and CoValidator and support programmable devices and reference boards from Altera, Xilinx, Memec/Insight and others.
 
CoDeveloper
CoDeveloper provides C to RTL design and compilation for various FPGA platforms including Xilinx and Altera. It enables you to create your own FPGA-based custom platform and to target systems with external processors, including DSPs.
     
 
Manhattan Routing is a privately held Silicon Alley based EDA company founded in February 1997. We provide a tool suite targeting the "Timing Closure" phase of the IC design flow through products that provide physical vizualisation capabilties to the front-end design teams, and a suite of physically aware timing report analysis functions together with associated fixing capabilties.
 
Timing Closure with Physical Window and Optimization Cockpit
Physical Window™/Optimization Cockpit™ (PW/OC) is a timing closure tool package that allow effective and timely closure of the last 100 violating paths of large high performance ASICs. Through the concept of a "timing sensitized layout" the tool suite enables analysis of the timing problems within the physical context. This functionality ranges from visualization of the timing paths in the physical domain to classification of timing problems based on the domain (logical or physical) of origin.
     
 
Mirabilis Design provides the Industry’s first fully-integrated, abstract-to-detail modeling and simulation application solution for electronics and embedded software. Architects can create a visual executable prototype of the proposed product and conduct ad hoc "what-if’s" to resolve feasibility issues and optimize for cost, performance and power.
 
VisualSim™
VisualSim™ Architect is used for conceptual exploration, performance analysis and architecture design of electronics and embedded systems. The pre-defined, parameterized library blocks and multi-domain simulation kernel enables engineers to design the digital, IC, embedded software, image processing, analog, DSP and control systems. The advantages of using VisualSim Architect are to create large models quickly, execute faster system simulations and standardize communications through visual specifications.
     
 
Orion Consulting provides advanced EDA technology to users worldwide. Our latest product, VRTL, is a unique front-end IC design solution that provides a method for generating synthesizable Verilog RTL code from graphically entered logic block schematics.
 
Graphical RTL design with VRTL Demo
This demo illustrates the benefits, features, and use of VRTL for rapid front-end RTL design. VRTL is a graphical design-entry tool capable of generating synthesizable Verilog RTL code from logic block schematics. Included is a demonstration of a FIFO being implemented with VRTL.
     
 
Posedge Software develops, sells, and supports EDA products and provides associated services. The first product introduced by Posedge is InnerLoop™, an Open Development Environment for Verilog, VHDL, SystemC, and other C/C++ applications for hardware design engineers, verification engineers, and EDA developers.
 
InnerLoop™ Product Demo
InnerLoop™ is an Open Integrated Development Environment for Verilog, VHDL, SystemC, C/C++, and many other languages, that runs on Linux, Solaris, and Windows. Engineers working on IC design, verification, EDA — as well as software development — use InnerLoop to navigate through various languages and optimize repeated execution of tools used during their development process. InnerLoop incorporates Visual SlickEdit® for editing (with key bindings for vi, emacs, and 8 other popular editors) and interfacing with configuration management systems (CVS, ClearCase, SourceSafe, Perforce, and others).
     
 
Prolific's IC design optimization software significantly reduces time to tapeout by automatically improving performance or reducing power consumption of cell-based designs. Prolific's customers include companies like AMD, NEC, ARM, and Broadcom. Prolific is a 10-year-old, privately held, profitable company based in Silicon Valley.
 
ProTiming™ Demo
ProTiming™ is an add-on for Synopsys PrimeTime® that automatically improves timing performance by an average of 10 percent by intelligently selecting, placing, or combining standard cells, even in designs previously optimized during the place-and-route flow.
     
 
Silicon Dimensions is developing tools that will streamline the integrated circuit (IC) design closure process -- allowing logic design engineers to more efficiently and cost-effectively plan the design of large ICs. These tools will address problems which result in design schedule slips, design closure issues, increased development costs and general frustration in the IC design closure process. The technology you can rely on for today's 180 nm and below high density technologies - developed by designer engineers for design engineers.