Demos On Demand


	SYSTEMC SEMINAR This seminar provides an in-depth review of new verification methods including Co-Simulation with SystemC, Co-Verification with ARM and other system-level design and verification techniques. Sessions are aimed at helping engineers transition to faster verification techniques using their current design flow by providing practical approaches to system-level design.

SystemC - Basic Ideas

Overview of the SystemC language, its history, structure and areas where
best utilized. Includes an understanding of the design flow, simulation and synthesis.

SystemC - ESL Design

Electronic System-level methodology applied to the complexity of digital designs that have grown dramatically in recent years and require a new approach.

SystemC - Synthesis

Includes a brief description of the tools and services for SystemC Synthesis from Celoxica, Aldec's partner in joint design solutions, also examines Design Abstraction, Synthesizable SystemC, and the Agility Compiler.

SystemC - Learning by Example

Provides a simple working example of the co-simulation principles together with with HDL presented in a side-by-side comparison.

SystemC - HDL Co-existence in Riviera

Using the Riviera software simulator, this section provides an example of how to make SystemC, VHDL and Verilog design blocks talk to each other.

SystemC - Data Types

An exploration of SystemC Data Types—2-value and 4-value logic types, integer types, and vector types.

SystemC - Design Elements

Covers modules and ports, signals and variables, processes, instantiations, and the sc_main function.

SystemC - Transaction Level Verification

The conclusion to the SystemC seminar uncovers how to start using SystemC in a typical design flow. Example is based on a working sample design.

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