This year's "undignified" topics were: Magma's P&R market share, Vic promoting outsourcing to India, ClearShape's exit strategy, Cadence Tcl/SKILL/Pcell, Ciranova, Open Access, the Synopsys-Magma lawsuit, the Year of SystemC, small vs. large DFM vendors, Brion, the Mentor donut problem, Virtuoso 6.1, CPF vs. UPF, Sequence power tools, the Forte CEO exit, Forte vs. Bluespec, PrimeTime vs. Cadence ETS, the Infineon Magma 2 day timing closure letter, Magma Quartz vs. Mentor Calibre vs. Cadence PVS, worst EDA market stats, death of Dataquest, EDAC vs. Gary, price wars, and is EDA stagnating? Enjoy!
The industry's first complete solution integrates logic design, verification,
and implementation technology—all enabled with the Si2 Common Power Format (CPF)—to improve
productivity, reduce risk, and achieve optimal trade-offs among timing, power, and area.
Virtuoso Constraint Flow (IC 6.1 release)
Explore how constraints can help designers manage their design environment. The demo will take you from design schematic into layout, and then into routing all in one, easy-to-use design cockpit
PyCell Studio™ & PCell Xtreme™
While interoperability has progressed rapidly in the digital domain, analog design has lagged, due in part to the lack of an interoperable PCell mechanism. This has made interoperability between multiple vendors' tools difficult. PyCell Studio helps reduce the time and cost of PCell and layout generator creation for deep submicron processes. PCell Xtreme enables the migration of PCells created in proprietary languages into multi-vendor OpenAccess flows. Together, PyCell Studio and PCell Xtreme provide a complete, interoperable OpenAccess PCell solution. Download PyCell Studio for free at www.ciranova.com.
The Move to Physical Synthesis
In this whiteboard discussion, Ken McElvain, Synplicity's founder and CTO, discusses the evolution of modern FPGAs to their present 65 nanometer form and what the implications are for the design of FPGAs in the future.
TotalRecall Full Visibility Technology
This whiteboard demonstrates the revolutionary new TotalRecall technology which enables you to debug and verify ASIC/SOC designs, ASSPs, and FPGAs at real hardware speed with full signal and state visibility.