Having a bad day? Your last chip required a respin, you just realized that there's a whole class of bugs that your testbench isn't set up to catch, and you don't have enough engineers to write all the tests you're going to need. Your only chance for survival: hitch a ride with a friendly team of verification experts for this seminar covering Testbench Automation, Reuse, and Functional Coverage.
  Introduction & Verification Methodology
This sessions focuses on an introduction to Mentor Graphics’ Advanced Verification Methodology (AVM), which greatly facilitates the development of transaction-level testbenches that can be used to verify designs at multiple levels of abstraction.

  Testbench Automation & Coverage
This session focuses on how to best implement re-usable verification components like generators, drives, monitors and scoreboards. Constrained-randomization and functional coverage are also covered. This section shows how to implement an efficient transaction based verification environment purely in SystemVerilog.

  Advanced Stimulus Generation
Currently, engineers often write directed tests to verify the functionality of their design. Once functionality has been verified they add more tests to the suite. This process is time consuming and leaves many corner cases untested. Rather than require tests to check each feature individually, constrained-random verification (CRV) allows a single test to check multiple features—each "test" checks many scenarios, and the simulator itself chooses a specific scenario for each invocation. This session provides the basics and best practices for writing efficient constrained-random stimulus with SystemVerilog for VHDL and Verilog designs.

  Formal analysis & clock-domain verification
When products are late, over budget, or functionally flawed your organization needs to improve its processes and/or practices. Adopting an advanced functional verification solution, such as Questa, increases productivity, predictability and quality. Augmenting this solution with comprehensive formal analysis and automated clock-domain crossing verification provides additional benefit, addressing the verification challenges of a design’s most critical and error-prone circuitry. This session provides an overview of these technologies, advice on how to get started using them, and an introduction to Mentor’s tools, 0-In Formal Verification and 0-In CDC.

  SystemVerilog Assertions
The SystemVerilog language enables several new verification methodologies which target increased verification productivity. Assertion Based Verification, or ABV, is a powerful methodology which increases verification productivity through improved bug detection/isolation as well as shortening the time required to debug design failures. Coverage Driven Verification, or CDV, increases verification productivity by providing true functional coverage metrics which can easily detect and report the occurrence of important test sequences and design corner-cases. This session provides examples of both assertions and functional coverage points.
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