Building a CapSense/USB Demo Using PSoC as FPGA Companion
Cypress PSoC Programmable Systems on Chip can be used as a cost-effective companion chip for a Xilinx FPGA device.
Flagship JasperGold™ unleashes formal verification on top project challenges spanning the IC development cycle.
Creating Complex HDI Designs
This demo will show Cadence’s Constraint-Driven HDI design flow in Allegro PCB Editor.
Active Design™ accelerates design creation and IP leverage with system and databases for RTL analysis.
Interview with Andrew Yang
Listen to Andrew Yang as he shares his view on what it takes for a company to survive and even grow during an economic downturn.
Interview with Piyush Sancheti
Join us for a discussion on semiconductor IP quality that covers the definition, current issues, existing metrics and tools.
Interview with Mike McNamara
Mike ("Mac") MacNamara discusses high-level synthesis (HLS) and its capabilities.
Interview with Kathryn Kranen
Kathryn Kranen discusses formal verification as a broad spectrum of applications.
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7/28/2010 - Jasper Design
Jasper Presenting "New Technologies In Formal Verification" at SAME 2010 Forum October 7
6/2/2010 - Jasper Design
Jasper Crosses the Design-to-Verification Chasm
5/18/2010 - Jasper Design
See Jasper Formal Verification in Action at DAC June 13-18, Booth 1337
4/20/2010 - Jasper Design
Jasper’s Kathryn Kranen Re-Elected As EDAC Vice Chair
Zazz™ from Zocalo Tech
Zazz enables designers to be key contributors to the Assertion Based Verification process and verification engineers to be more effective.
A suite of tools that capture and validate embedded system specifications.
Mentor gathered a team of verification experts whose presentations provide guidance on Testbench Automation, Reuse, and Functional Coverage.
Common Platform alliance members, Chartered, IBM and Samsung, jointly hosted the first-ever Common Platform Technology Forum.
This 12 session Bluespec SystemVerilog training course is the standard intro that Bluespec provides to their customers.
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