CYPRESS: Building a CapSense/USB Demo Using PSoC as FPGA Companion Cypress PSoC Programmable Systems on Chip can be used as a cost-effective companion chip for a Xilinx FPGA device.   TENSILICA: Diamond Standard Series Software Diamond Standard Series is a set of six off-the-shelf synthesizable cores ranging from low-power controllers to high-performance DSPs.   CADENCE: Metric Driven Verification 101 Learn how to implement a metric driven verification environment to improve predictability, productivity, and quality of your chip development.   JASPER: Liberate™ and Variety™ New Active Design™ delivers an analysis system and databases for design deevelopment and reuse. APACHE: Interview with Andrew Yang Listen to Andrew Yang as he shares his view on what it takes for a company to survive and even grow during an economic downturn. ATRENTA: Interview with Piyush Sancheti Join us for a discussion on semiconductor IP quality that covers the definition, current issues, existing metrics and tools. CADENCE: Interview with Mike McNamara Mike ("Mac") MacNamara discusses high-level synthesis (HLS) and its capabilities.   JASPER: Interview with Kathryn Kranen Kathryn Kranen discusses formal verification as a broad spectrum of applications. EMAIL ADDRESS USERNAME PASSWORD Forgot your password? Become a DOD member! 5/19/2009 - Jasper Design ARM Selects Jasper for Formal Verification of IP 4/30/2009 - Cadence Cadence Kicks Off Worldwide User Conferences with CDNLive! EMEA 2009 4/27/2009 - Jasper Design Jasper, AMD Ink Long-Term Formal Verification Deal 4/21/2009 - Apache Apache Design Solutions Introduces Totem, the Industry’s First Power and Noise Integrity Platform for Analog and Mixed-Signal Designs       ZOCALO: Zazz™ from Zocalo Tech Zazz enables designers to be key contributors to the Assertion Based Verification process and verification engineers to be more effective.     BEACH SOLUTIONS: EASI-Studio™ A suite of tools that capture and validate embedded system specifications.   Mentor gathered a team of verification experts whose presentations provide guidance on Testbench Automation, Reuse, and Functional Coverage.     BLUESPEC SystemVerilog Training This 12 session Bluespec SystemVerilog training course is the standard intro that Bluespec provides to their customers.
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