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Hear the bigwigs discuss controversial topics like: Is SystemC a pipe dream? What about Cadence Open Access vs. Synopsys Milkyway? Are the Vera vs. Specman "e"
wars re-igniting or was Cadence foolish to acquire Verisity? What's the latest dirt in the layout wars? What caused Monterey and AmmoCore to die?
Panelists:
• Rajeev Madhavan - CEO, Magma
• Pravin Madhani - CEO, Sierra Design
• Jacob Jacobsson - CEO, Forte
• Antun Domic - VP, Synopsys
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• Robert Hum - VP, Mentor Graphics
• Ted Vucurevich - CTO, Cadence
• Gabe Moretti - Technical Editor, EDN
• Gary Smith - Gartner/Dataquest
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Rhines explores how verification has seen successive waves of innovation, moving up the layers of abstraction. Now, new techniques will support more effective verification at the multiple
levels required for advanced SoC design—at the block, intra-block and system level. These innovations are supported by the emergence of standards, ensuring the long-term viability of the advancements.
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With all the new languages and methods, what plans are there for adapting existing or adopting new methodology and process flows? Panelists answer these questions: Is there one right answer?
Are there multiple paths? Some of the issues covered include:
• How important are language(s)?
• What is the right level of abstraction?
• Is there a need to design for verification?
• What new methods are being adopted: assertion-based verification, coverage-driven verification, transaction-level modeling, constrained-random stimulus generation and hardware/software co-verification?
• Is it feasible to create reactive testbenches?
• Where are the bottlenecks now?
Moderator: Stephen Bailey
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Panelists:
• Robert Cram - Gennum
• Wolfgang Ecker - Infineon
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• Richard Ho - Mentor Graphics
• Carey Kloss - Cisco Systems
• Satu Lummevuo - Nokia
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To help designers face ever more extreme verification challenges, changes must be made. Decisions must be made about organizational structure (separate design/verification teams vs. designers who also verify),
specifications, reuse, level of abstraction, how to work with EDA and IP vendors, etc. This panel explores why so much time is being spent in functional verification, as well as:
what cultural and organizational changes must take place to bring quality back to the forefront of design? Where is the measurable proof of quality? How much can we improve
overall quality and reduce verification time—and what would this take to do it?
Moderator: Gabe Moretti
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Panelists:
• Gary Smith - Gartner Dataquest
• Harry Foster - Jasper Design Automation
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• Kevin Normoyle - Azul Systems
• Limor Fix - Intel Semiconductors
• Andrew Piziali - Verisity Design
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Driven by chipset and IP providers, Europe, an early adopter of ESL and SystemC, has established groups and initiatives to set standards to drive even wider adoption for ESL.
And, in the East, Japan is fast moving into production on the merits of the SystemC language "as-is"—with little methodology infrastructure.
The US, however, still lags as more emphasis is placed on SystemVerilog. This panel reviews the status of ESL in the US, challenges to US leadership, and the strategies
for expanding ESL in the US for System-on-Chip modeling, design and verification.
Moderator: Gary Smith
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Panelists:
• Emil Girczyc - Summit Design
• Brett Cline - Forte Design Systems
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• H. Tony Chin - HD Labs
• Maurizio Vitale - Philips
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Presenters:
• Ben Cohen - VhdlCohen Publishing
• Alex Fasan - Synopsys
• John Girard - Synopsys
• Jin Hou - Synopsys
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Presenters:
• Victor Berman - Cadence
• Erich Marschner - Cadence
• Lisa Piper - Cadence
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Presenters:
• Stephen Bailey - Mentor
• Tom Fitzpatrick - Mentor
• Michael Horne - Verifica
• Dave Rich - Mentor
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• 1.1 Verification IP Qualification and Usage Methodology for Protocolcentric SoC Design
• 1.2 New Trends and Methodologies in FPGA Simulation
• 1.3 Efficient Test Stimulus Methodology for SystemC Based Verification Testbench
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• 2.1 Signed Arithmetic in Verilog 2001 - Opportunities and Hazards
• 2.2 Fixed- and Floating-Point Packages for VHDL 2005'
• 2.3 A New Ultimately Flexible Discrete Convolution Architecture
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• 3.1 A Methodology for Verifying Sequential Reconvergence of Clock-Domain Crossing Signals
• 3.2 Developing Transaction Level Models for Verification
• 3.3 Using MatLab and Simulink in a SystemC Verification Environment
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• 4.1 Data Abstraction is the Beginging of Algorithm Abstraction
• 4.2 IEEE 1850 PSL: The Next Generation
• 4.3 VHDL-200x: The Future of VHDL
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• 5.1 PSL and SVA: Two Standard Assertion Languages Addressing Complimentary Engineering Needs
• 5.2 Five Hot Spots for Assertion-Based Verification
• 5.3 Practical Implementation of Assertion Based Verification for Flash Design
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• 6.1 Untimed-C based SoC Architecture Design Space Exploration for 3G and Beyond Wireless
• 6.3 Merging ASIC and FPGA Design Practices to Cut Cycle Time
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• 7.1 An Incremental Approach to Measuring Coverage
• 7.2 Coverage Guided Generation Of Random Instruction Streams For The Verification Of Application Specific Instruction Set Processors
• 7.3 Applying Code Coverage to Increase Verification Effectiveness
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• 8.1 Simplifying Complex IP Design with a Hierarchical Modular, Mixed-Language Approach
• 8.2 Guidelines for SystemVerilog Assertion IP Development
• 8.3 Function Verification of Design IP - Trust or Hard Work?
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• 9.1 Adopting Assertion Based Verification with PSL
• 9.2 Adopting Assertions Incrementally to Enhance Your Verification Methodolgy
• 9.3 Off-Line Debugging and Testing of On-Line Checkers
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• 10.1 Modeling a Highly Generic Processing Unit Using SystemVerilog
• 10.2 Using SystemVerilog Now with DPI
• 10.3 SystemVerilog Interop Score Card
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