New York, NY, 3/23/04 — Manhattan Routing Inc. (MRI) today announced that its Physical Window design visualization environment enabled ChipWrights Inc., a fabless semiconductor company, to meet timing specifications and significantly reduce the tapeout schedule for a 0.18-micron image processing DSP chip.

The high-performance 200MHz ASIC design had 1.5 million logic gates and was manufactured on a 6-metal-layer, 0.18-micron process technology. The design contained a significant number of high-speed data paths from logic to memory, making almost all timing on the chip critical in order to meet performance. Physical Window allowed the logic designers to explore the physical implementation of the datapath and guide the implementation team to an effective original floorplan that would meet both density and timing requirements.

"Physical Window gave us tremendous bang for the buck, said Mike Goldman, director of engineering at ChipWrights. It was a cost-effective method for communicating with our vendor's physical implementation team. Without Physical Window, we would have had to either be on-site at the vendor every time we needed to view the layout, or else purchase expensive layout tools to do it in-house.

Using Physical Window, ChipWrights was also able to meet the chips target timing performance specification. They also shaved time off the physical design schedule by identifying poor placement of several timing-critical hierarchical modules early in the design process. Due to the promptness and quality of MRIs technical support, not only did we uncover design issues and increase the chips performance, but also we didnt lose valuable schedule time by waiting for the resolution of tool issues, added Goldman.

Our goal is to support our customers in reducing the risks inherent in physical implementation, as well as reduce time-to-tapeout, said Tor Ekenberg, president of MRI. Fabless semiconductor companies who outsource physical design have very specific communication challenges with their implementation vendors. Were thrilled that ChipWrights received value in a real tape-out using our products. They were able to work very closely with their vendor, and in the process, saved enormous amounts of time and money and ended up with a better chip.

More About Physical Window: Physical Window is a design visualization environment for chip implementation front-end teams that offers a cost-effective solution for accelerated design management. PW is designed to merge the physical details of the layout data and the timing reports from sign-off tools such as Synopsys PrimeTime and Cadences Pearl. As a result, logic designers can better understand the physical implementation causes of timing violations and provide feedback to physical designers to reach timing closure, faster.

About ChipWrights (http://www.chipwrights.com): ChipWrights is a fabless semiconductor company specializing in the design, development, and marketing of a new class of digital signal processing (DSP) devices called visual signal processors (ViSPs). Built on an innovative architecture comprising a RISC processor and a highly integrated, scalable array of DSP vector processing units, this fully programmable, low cost, low power, and very high performance system-on-chip (SoC) family is ideal for building competitive products in the mobile digital imaging and video markets. Applications range from real-time image capture/presentation to image transmission/network media infrastructure. ChipWrights provides a complete software development tool suite and hardware reference designs. Headquartered in the United States, the company has offices in Waltham, MA and Tokyo, Japan.

About Manhattan Routing
Manhattan Routing Inc. (MRI) is a privately held EDA company providing tools for physical design visualization and timing closure of large, high-performance ASICs. MRI's tools are based on tape-out proven technology that has been used on more than 30 ICs, developed both by MRI's services group and customers. The Physical Window/Optimization Cockpit tool suite bridges the gap between physical designers and logic designers during the timing closure phase of the IC design process. MRI also provides design services in the physical implementation area. The company is located in New York City's Silicon Alley.