Blaze Torch Technology Demonstration
The Blaze "Torch" lithography-aware analysis and optimization technology enables chip designers to model and compensate for litho-induced process variations when working with silicon technologies of 65nm and below. Blaze Torch technology employs the production-OPC "Halo" lithography simulation engine to model the effects of process variations on power and performance. It uses built-in timing and power optimization algorithms to automatically compensate for these variations. It also identifies litho hot-spots that could lead to physical defects, and produces a repair guidance file for automatic defect repair using third-party physical design tools.
High-performance Custom Routing and DFM Optimization for Advanced Process Nodes using the Cadence® Space-based Router and Chip Optimizer
View the all new innovative space-based gridless analysis driven routing and yield optimization solutions from Cadence Design Systems. The Cadence Space-based Router and Cadence Chip Optimizer deliver a silicon proven full-chip routing and DFM optimization solution that provide concurrent design and manufacturing convergence for improved design performance, manufacturability and yield at 65nm and below processes. The demo features the Cadence Space-based Router which is a custom IC high capacity, high performance convergent design routing solution for custom digital and analog mixed signal designs. The demo also features the Cadence Chip Optimizer, which is complimentary to the Cadence Space-based Router or any IC design routing solution for post-route model driven manufacturing and yield optimization.