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BACK END DESIGN:  Physical Design
These demos present an in-depth view of various back end design products relative to physical design. Scroll down to view all demos or select a vendor name from either menu.
 
Accelicon Apex Design Systems Cadence Ciranova ClioSoft Golden Gate Tech Manhattan Routing Prolific
Sequence Design Silicon Canvas Tanner EDA ViASIC
MQA (SPICE Model Quality Assurance) Demo
Model Quality Assurance (MQA) automatically assesses the quality of foundry-supplied models, generates the documentation, and compares multiple model libraries, versions, and SPICE platforms. Model Builder Program (MBP) generates and optimizes SPICE models using data from silicon wafer testing.

     
Compex-RT Demo
Compex-RT is a space propagation tool for improving routability and/or achieve die size reduction. This demo will include Compex-RT's usable space analysis, routability analysis, timing analysis, and space propagation for improved routability and die size reduction.

     
Front to Back Constraint-Driven PCB Design Flow
This demo will show how Allegro Constraint Driven PCB design flow allows engineers to embed constraints within their design and enable a constraint driven PCB layout flow to avoid unnecessary physical prototype iterations.

     
Advanced Virtuoso Design Environment (IC 6.1 release)
This demo focuses on the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment. You will discover some of the new features and functionality that are available, focusing on the enhanced productivity that designers enjoy with the introduction of assistance. You will also learn about the constraint management system that can be used to pass information the schematic through to layout.

NOTE: This demo requires 1280 x 1024 Minimum Screen Resolution and a Minimum 400 Kbps network connection. In addition, a faster computer (1Ghz+, 512K RAM) is recommended for optimal playback.

     
 
Accelerated Physical Design with Virtuoso Prototype Flow (IC 6.1 release)
Discover the new, common cockpit that integrates all the Virtuoso products designers can access at any point and time during the design. You will see how to quickly perform area estimation on a piece of data, obtain the information, and plug it into a floor planning technology. You will also see simple editing to correct violations, the use of pin placement technology, and design optimization.

 
     
 
Virtuoso Constraint Flow (IC 6.1 release)
Explore how constraints can help designers manage their design environment. The demo will take you from design schematic into layout, and then into routing – all in one, easy-to-use design cockpit.

 
     
 
High-performance Custom Routing and DFM Optimization for Advanced Process Nodes using the Cadence® Space-based Router and Chip Optimizer
View the all new innovative space-based gridless analysis driven routing and yield optimization solutions from Cadence Design Systems. The Cadence Space-based Router and Cadence Chip Optimizer deliver a silicon proven full-chip routing and DFM optimization solution that provide concurrent design and manufacturing convergence for improved design performance, manufacturability and yield at 65nm and below processes. The demo features the Cadence Space-based Router which is a custom IC high capacity, high performance convergent design routing solution for custom digital and analog mixed signal designs. The demo also features the Cadence Chip Optimizer, which is complimentary to the Cadence Space-based Router or any IC design routing solution for post-route model driven manufacturing and yield optimization.

 
     
 
Solving D/MS Design Challenges with Virtuoso AMS Designer
Discover how you can effectively design mixed-signal chips, regardless of design size. Virtuoso AMS Designer is the latest technological break through that brings the power of behavioral modeling to the IC designer. It tackles the difficult challenge of converging massive digital designs with precise analog circuitry and simulating them accurately and quickly, while using Verilog-AMS/VHDL-AMS languages, Virtuoso Schematic Editor schematics, Assura™ extracted views, timing views from SoC Encounter, and textual descriptions for NC-Sim. (This demo features custom design products from IC 5.1.41 release)

 
     
 
PyCell Studio™ & PCell Xtreme™
While interoperability has progressed rapidly in the digital domain, analog design has lagged behind, due in part to the lack of an interoperable PCell mechanism. This has made interoperability between multiple vendors' tools difficult. PyCell Studio helps designers reduce the time and cost of PCell and layout generator creation for deep submicron processes. PCell Xtreme enables the migration of PCells created in proprietary languages into multi-vendor OpenAccess flows. Together, PyCell Studio and PCell Xtreme provide a complete, interoperable OpenAccess PCell solution. Download PyCell Studio for free at www.ciranova.com. (video available to all Demos on Demand members)

 
     
 
Streamlining Design Team Collaboration with ClioSoft DM Solutions
ClioSoft is a leading provider of design data management solutions for the electronics design industry. The multi-site development environment and cross-platform support enables global team collaboration and efficient management of design data and processes from concept to tape-out. ClioSoft's SOS Data Collaboration Platform is integrated with EDA tools from leading vendors and provides seamless data management solutions for RTL, Cadence® IC, and Mentor Graphics® IC design flows.

 
     
 
Power Plan Gold™ and Power Optimize Gold™
Power Plan Gold (PPG) efficiently creates complex power grids with unique Parametric Templates™ technology, PPG natively supports multiple supplies, analyzes the power grid for IR drop and EM violations and automatically repairs the grid. Power Optimize Gold automatically reduces power consumption by 15 – 20% or more using a proprietary WiresFirst™ algorithm while maintaining timing, SI, and EM constraints.

 
     
 
Timing Closure with Physical Window and Optimization Cockpit
Physical Window™/Optimization Cockpit™ (PW/OC) is a timing closure tool package that allow effective and timely closure of the last 100 violating paths of large high performance ASICs. Through the concept of a "timing sensitized layout" the tool suite enables analysis of the timing problems within the physical context. This functionality ranges from visualization of the timing paths in the physical domain to classification of timing problems based on the domain (logical or physical) of origin.

 
     
 
ProTiming™ Demo
ProTiming™ is an add-on for Synopsys PrimeTime® that automatically improves timing performance by an average of 10 percent by intelligently selecting, placing, or combining standard cells, even in designs previously optimized during the place-and-route flow.

 
     
 
PHYSICALSTUDIO™ - Concurrent Design Closure
Proven in more than 100 tapeouts at feature sizes down to 90 nanometers, the concurrent analysis-based optimization of timing, SI, voltage drop, and leakage power provided by PhysicalStudio continues to win converts with leading designers worldwide.

 
     
 
Silicon Canvas Laker L-series
LAKER is a high productivity next generation custom layout tool. It contains the full-fledged traditional polygon editing features to provide the greatest flexibility and controllability, yet it offers many intelligent guidance and automation to make the layout creation, editing tasks much more efficient and productive. With LAKER, users are able to complete the layout designs and achieve the desired layout density and performance 2 to 6 times faster than using other layout editors.

 
     
 
HiPer Silicon™ for Analog/Mixed Signal IC Design
See Tanner EDA’s HiPer Silicon™ in action – a complete IC design suite consisting of tools for schematic capture, circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. Learn how HiPer Silicon can help you increase productivity and speed your design concept to silicon.

 
     
 
Empowering SOC Reuse with ViaMask and ViaPath
This demo provides a detailed tour of ViaMask™, an embeddable one-mask structured ASIC fabric that in conjunction with ViaPath, an easy to use physical implementation software package, empowers you to reuse your valuable IP to serve multiple derivative applications.

 
     


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