These demos present an in-depth view of various back
end design products relative to post layout analysis.
Scroll down to view all demos or select a vendor name
from either menu.
AWR SI™ Design Suite
The AWR SI Design Suite combines the unique AWR design platform and
unified data model with a signal integrity analysis environment, providing comprehensive, easy-to-use analysis capabilities that work
seamlessly in one integrated platform. The solution supports multiple process technologies, enabling concurrent design and signal
integrity analysis of complex interconnects spanning chip, package, module, and PCB design boundaries.
Incentia TimeBench Environment TimeCraft is the fastest gate-level full-chip static timing analyzer in market today.
It contains industry leading features for nanometer designs, including location-based on-chip-variation, parallel multi-mode multi-corner
timing analysis, and signal integrity analysis for crosstalk and noise.
Challenges and Solutions for Verification of Post-Layout Nanometer Designs
Simon Young, Product Line Director To lower cost and improve the chances of silicon
success, IC's manufactured in 130 nanometer processes
and below must analyze the effects that can prevent
design success. Drivers for using nanometer processes,
and the challenges for verification are discussed in
this presentation. Topics include reliability of power
and signal networks; the timing impact of dynamic voltage
drop in power networks; dynamic crosstalk noise due
to coupling capacitance; and MOSFET device reliability.
Signal Integrity Design Assistants
SIDEA™ (Signal Integrity Design Assistants) is a complete
suite of signal integrity design assistants for parasitic
extraction and S-parameter conversion, manipulation
and modeling. SIDEA was developed to put most-often
used signal integrity design tools in one place so engineers
need not mix and match software from various sources.
COOLTIME™ - Like, Instantaneous,
Dude
The "way cool" tool to see this year is CoolTime, providing
electrical integrity analysis for the concurrent analysis
of power, voltage drop, timing, and signal integrity.
With an emphasis on instantaneous voltage drop, it overcomes
limitations of existing static IR-drop tools.
PHYSICALSTUDIO™ - Concurrent Design Closure
Proven in more than 100 tapeouts at feature sizes down
to 90 nanometers, the concurrent analysis-based optimization
of timing, SI, voltage drop, and leakage power provided
by PhysicalStudio continues to win converts with leading
designers worldwide.
