These demos present an in-depth view of various back
end design products relative to physical synthesis.
Scroll down to view all demos or select a vendor name
from either menu.
Compex-RT Demo
Compex-RT is a space propagation tool for improving routability and/or
achieve die size reduction. This demo will include Compex-RT's usable
space analysis, routability analysis, timing analysis, and space propagation
for improved routability and die size reduction.
SoC Encounter Global Physical Synthesis (GPS)
SoC Encounter GPS is a high-capacity RTL-to-GDSII system that enables fast timing closure on complex, multimillion-gate chips by determining early on whether a design will meet its performance, area, and power targets. SoC Encounter GPS combines globally focused RTL synthesis, silicon virtual prototyping, SI-aware routing, and signoff/SI analysis into a single system.
Encounter Front-end Design Flow
Build smaller, faster, lower power, and higher quality designs in less time with the Encounter front-end design flow, which incorporates Encounter RTL Compiler global synthesis, Encounter Test, and Encounter Conformal Equivalence Checker. Using the flow, you'll get high quality of silicon(QoS) in terms of speed, area, and power with wires; greater accuracy for fast yield ramp; and the most comprehensive solution for equivalence checking.
Timing Closure with Physical Window and Optimization Cockpit
Physical Window™/Optimization Cockpit™ (PW/OC) is a timing closure tool package that allow effective and
timely closure of the last 100 violating paths of large high performance ASICs. Through the concept of a "timing
sensitized layout" the tool suite enables analysis of
the timing problems within the physical context. This
functionality ranges from visualization of the timing
paths in the physical domain to classification of timing
problems based on the domain (logical or physical) of
origin.
The Move to Physical Synthesis In this whiteboard discussion, Ken McElvain, Synplicity's founder and CTO, discusses the evolution of modern FPGAs to
their present 65 nanometer form and what the implications are for the design of FPGAs in the future.
Synplify® Premier Advanced FPGA Physical Synthesis and Debug
This video provides an overview of Synplicitys patented graph-based physical synthesis technology and introduces Synplify Premier software, the ultimate FPGA design and debug solution.
Amplify® ISSP™ Physical Synthesis™ Demo This in-depth video demonstrates Synplicity's Amplify ISSP software, a high-performance physical synthesis tool optimized specifically for the ISSP architecture.
Synplify DSP
The Synplify DSP solution accepts algorithmic specifications from such tools as MATLAB®/Simulink®,
and automatically generates high-quality, optimized RTL for hardware implementation.
Identify™ RTL Debugger
The Identify tool is the only software that allows FPGA
and ASIC prototyping designers to functionally debug
their hardware directly in their RTL source code. In
this demonstartion, you will see how Identify software
reduces your hardware debug time by providing an easy
and fast RTL-based debug environment. For FPGA design
or ASIC prototyping, Identify software provides the
quickest way to find bugs in your hardware.
ZenTime
This demo shows how ZenTime eliminates negative slack in cell-based designs and boosts design performance
by over 15 percent. You'll also see how ZenTime allows you to close timing in days instead of months while
utilizing your existing cell-based flow and high-yield technology.
