Front to Back Constraint-Driven PCB Design Flow
This demo will show how Allegro Constraint Driven PCB design flow allows engineers to embed constraints within their design and enable a constraint driven PCB layout flow to avoid unnecessary physical prototype iterations.
Solving New Challenges in Nanometer Design with Assura Physical Verification
In nanometer design, physical verification including layout parasitic extraction is a must to achieve manufacturing
sign-off. This demonstration features the use of Assura RCX, the industry’s standard for 3D device-level parasitics
extraction, to accurately extract and optimize the on-chip parasitics of a VCO block generating an Extracted View
with parasitics for subsequent simulation of a digital/mixed-sign design. An overview of the Assura DRC, LVS for nanometer
designs will also be presented. (This demo features a previous release of Assura physical verification).
HiPer Silicon for Analog/Mixed Signal IC Design
See Tanner EDA’s HiPer Silicon in action – a complete IC design suite consisting of tools for schematic capture,
circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. Learn how HiPer Silicon can help you increase productivity and
speed your design concept to silicon.