These demos present an in-depth view of various back end design products relative to physical verification.
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Solving New Challenges in Nanometer Design with Assura™ Physical Verification
In nanometer design, physical verification including layout parasitic extraction is a must to achieve manufacturing
sign-off. This demonstration features the use of Assura RCX, the industry’s standard for 3D device-level parasitics
extraction, to accurately extract and optimize the on-chip parasitics of a VCO block generating an Extracted View
with parasitics for subsequent simulation of a digital/mixed-sign design. An overview of the Assura DRC, LVS for nanometer
designs will also be presented. (This demo features a previous release of Assura physical verification).
Challenges and Solutions for Verification of Post-Layout Nanometer Designs
Simon Young, Product Line Director To lower cost and improve the chances of silicon success, IC's manufactured in 130 nanometer processes
and below must analyze the effects that can prevent design success. Drivers for using nanometer processes,
and the challenges for verification are discussed in this presentation. Topics include reliability of power
and signal networks; the timing impact of dynamic voltage drop in power networks; dynamic crosstalk noise due
to coupling capacitance; and MOSFET device reliability.
HiPer Silicon™ for Analog/Mixed Signal IC Design
See Tanner EDA’s HiPer Silicon™ in action – a complete IC design suite consisting of tools for schematic capture,
circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. Learn how HiPer Silicon can help you increase productivity and
speed your design concept to silicon.
