Hardware Platform-Based Design Using ARM PrimeCell Technology Ben Cade, ARM
This presentation discusses the steps involved in hardware platform creation. Beginning at the
product requirements capture phase, identified are key functional components and mapping these to both internal and external IP. The work flow from IP selection
through configuration and optimization to final implementation ready delivery is covered and uses a variety of ARM® processors and PrimeCell® IP
to demonstrate how to take full advantage of both the methodology and the AMBA® protocol.
Celoxica Software-Compiled System Design: JPEG2000 Case Study
This on-line demo walks through a design example
from specification to FPGA implementation showing the Software-Compiled System Design
methodology. The demo provides a detailed review of the Celoxica DK Design Suite environment
as applied to the development of an image processing system based on a JPEG2000 algorithm.
This in-depth demo shows how CoFluent Studio enables developers to define the right architecture early in their projects. You'll see how to model and simulate the system’s real-time application with time properties in a hardware/software-agnostic way from C/C++ code entry. Next, we'll simulate at high abstraction level the execution of the application and inter-processor communications on different models of hardware platforms to obtain prospective performance figures. Last, you'll see how to generate the C code for the software tasks of the application model on a RTOS.
CoDeveloper provides C to RTL design and compilation
for various FPGA platforms including Xilinx and Altera.
It enables you to create your own FPGA-based custom
platform and to target systems with external processors,
VisualSim - System-level Performance Analysis and Architecture Design
VisualSim™ Architect is used for conceptual exploration, performance analysis and architecture design of electronics and embedded systems.
The pre-defined, parameterized library blocks and multi-domain simulation kernel enables engineers to design the digital, IC, embedded software, image processing,
analog, DSP and control systems. The advantages of using VisualSim Architect are to create large models quickly, execute faster system
simulations and standardize communications through visual specifications.
This demo provides an intimate view of our Random
Architecture Verification Engine (RAVEN). The demo shows how RAVEN does far more than
simply verify the instruction set architecture. Its advanced controls and deep knowledge
allows processor validation of multithreading, multiprocessing, parallel instructions,
processor synchronization, cache coherency, and more.
OPENCORES Open RISC demo
The Open RISC embedded processor platform shows both the
features and full development platform available from OpenCores. The open source, Open RISC
1200 processor is highlighted along with the complete GNU development tool chain
including a running applications and booting Linux.
Summit Visual ESL & Embedded System Co-design Demo
This in-depth demo shows how Visual Elite ESC
provides a complete HW/SW verification environment utilizing SystemC, with an integrated ISS
that's linked with vendor-specific tools. You'll see how Visual Elite ESC interfaces
with ISS at a signal-level or transaction-level for higher performance—while providing fully
synchronized, HW and SW debugging and visibility.