These demos present an in-depth view of various design
products relative to embedded systems. Scroll down to
view all demos or select a vendor name from either menu.
ADVEDA MISS UNIVERS DEMO
Miss Univers is a complete HW/SW co-verification
tool for multi-processor SOC architectures, offering extensive debug capabilities, fast
simulation and emulation support. It includes an RTL simulator as well as a multi-core
IDE with most fascinating debug features and configurable user-friendly graphical
user interface.
Nios II Embedded Processor
Altera introduces the Nios® II family of embedded processors, extending the performance
and lowering the cost of the world’s most popular soft embedded processor. Designed
for use in Altera's Stratix® II, Stratix, Cyclone™, and HardCopy® device families,
Nios II designers can achieve performance over 200 DMIPS and spend as little as 35
cents on logic. With three processors and over 60 intellectual property (IP) cores
from which to choose, Nios II systems provide the ultimate in versatility, letting designers
create the perfect fit for their embedded system needs.
Hardware Platform-Based Design Using ARM PrimeCell Technology Ben Cade, ARM
This presentation discusses the steps involved in hardware platform creation. Beginning at the
product requirements capture phase, identified are key functional components and mapping these to both internal and external IP. The work flow from IP selection
through configuration and optimization to final implementation ready delivery is covered and uses a variety of ARM® processors and PrimeCell® IP
to demonstrate how to take full advantage of both the methodology and the AMBA® protocol.
Celoxica Software-Compiled System Design: JPEG2000 Case Study
This on-line demo walks through a design example
from specification to FPGA implementation showing the Software-Compiled System Design
methodology. The demo provides a detailed review of the Celoxica DK Design Suite environment
as applied to the development of an image processing system based on a JPEG2000 algorithm.
COFLUENT STUDIO
This in-depth demo shows how CoFluent Studio enables developers to define the right architecture early in their projects. You'll see how to model and simulate the system’s real-time application with time properties in a hardware/software-agnostic way from C/C++ code entry. Next, we'll simulate at high abstraction level the execution of the application and inter-processor communications on different models of hardware platforms to obtain prospective performance figures. Last, you'll see how to generate the C code for the software tasks of the application model on a RTOS.
CoDeveloper
CoDeveloper provides C to RTL design and compilation
for various FPGA platforms including Xilinx and Altera.
It enables you to create your own FPGA-based custom
platform and to target systems with external processors,
including DSPs.
VisualSim™ - System-level Performance Analysis and Architecture Design
VisualSim™ Architect is used for conceptual exploration, performance analysis and architecture design of electronics and embedded systems.
The pre-defined, parameterized library blocks and multi-domain simulation kernel enables engineers to design the digital, IC, embedded software, image processing,
analog, DSP and control systems. The advantages of using VisualSim Architect are to create large models quickly, execute faster system
simulations and standardize communications through visual specifications.
RAVEN Demo
This demo provides an intimate view of our Random
Architecture Verification Engine (RAVEN). The demo shows how RAVEN does far more than
simply verify the instruction set architecture. Its advanced controls and deep knowledge
allows processor validation of multithreading, multiprocessing, parallel instructions,
processor synchronization, cache coherency, and more.
OPENCORES Open RISC demo
The Open RISC embedded processor platform shows both the
features and full development platform available from OpenCores. The open source, Open RISC
1200 processor is highlighted along with the complete GNU development tool chain
including a running applications and booting Linux.
Summit Visual ESL & Embedded System Co-design Demo
This in-depth demo shows how Visual Elite ESC
provides a complete HW/SW verification environment utilizing SystemC, with an integrated ISS
that's linked with vendor-specific tools. You'll see how Visual Elite ESC interfaces
with ISS at a signal-level or transaction-level for higher performance—while providing fully
synchronized, HW and SW debugging and visibility.
Diamond Standard Series Software Toolchain
This demo highlights the easy-to-use software development tools for Tensilica’s Diamond Standard family of processor cores,
a set of six off-the-shelf synthesizable cores that range from area-efficient, low-power controllers to high-performance DSPs. The Diamond Standard Processor software development
tools include a complete compiler toolchain, instruction set simulator, performance analysis tools and project management tools.
