These demos present an in-depth view of various design products relative to FPGA tools. Scroll down to view
all demos or select a vendor name from either menu.
Quartus II Software Overview
The Quartus® II software is the only design environment available that supports FPGA, CPLD, and structured ASIC
HardCopy™ device designs. The following demonstration will show how easy it is to get started using the Quartus
II software as well as highlight what’s new in the latest
version of the software.
Basic FPGA/CPLD Design
The Altera® Quartus® II design software provides a complete, multiplatform design environment that easily adapts to your specific design needs.
It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes solutions for all phases of FPGA and CPLD design from design entry and
HDL synthesis to verification and programming. These demonstrations show the basic design procedures in the Quartus? II software.
Design Flows
The Quartus® II software supports many design flows to help you design for systems-on-a-programmable-chip and reach timing closure faster.
Design Optimization & Implementation
The Quartus® II software optimizes design performance
to reach timing closure faster. These demonstrations
provide an overview of available Quartus II features
that will help optimize design performance.
Shortening Design Cycles
The Quartus® II software provides many features to help
reach timing closure faster. These demonstrations give
an overview of some of the features available in the
Quartus II software to shorten overall design cycles.
Verification
The Quartus II software provides many features to help verify the functionality of any design and debug any
issues. These demonstrations provide an overview of some of the verification features available in the Quartus
II software.
Nios II Embedded Processor
Altera introduces the Nios® II family of embedded processors, extending the performance and lowering the cost of the
world’s most popular soft embedded processor. Designed for use in Altera’s Stratix® II, Stratix, Cyclone™,
and HardCopy® device families, Nios II designers can achieve performance over 200 DMIPS and spend as little
as 35 cents on logic. With three processors and over 60 intellectual property (IP) cores from which to choose,
Nios II systems provide the ultimate in versatility, letting designers create the perfect fit for their embedded
system needs.
CoDeveloper
CoDeveloper provides C to RTL design and compilation
for various FPGA platforms including Xilinx and Altera.
It enables you to create your own FPGA-based custom
platform and to target systems with external processors,
including DSPs.
TotalRecall™ Full Visibility Technology
This whiteboard demonstrates the revolutionary new TotalRecall technology which enables you to debug and verify ASIC/SOC designs, ASSPs, and FPGAs at real hardware speed with full signal and state visibility.
The Move to Physical Synthesis
In this whiteboard discussion, Ken McElvain, Synplicity's founder and CTO, discusses the evolution of modern FPGAs to
their present 65 nanometer form and what the implications are for the design of FPGAs in the future.
True DSP Synthesis
This whiteboard discussion introduces the concept of True DSP synthesis and how it is
different from other methods of going from DSP algorithm to RTL code for hardware
implementation. This discussion covers topics including design languages,
the importance of a technology-independent flow, and automatic application of DSP
synthesis optimizations.
Synplify® Premier Advanced FPGA Physical Synthesis and Debug
This video provides an overview of Synplicity’s patented graph-based physical synthesis technology and introduces Synplify Premier software, the ultimate FPGA design and debug solution.
Synplicity Synplify Pro® Advanced FPGA Synthesis Explore the Synplify Pro® solution,
the fast and efficient FPGA synthesis tool which can
be applied to a variety of target devices. The video
demonstrates success in meeting both timing and area
specifications.
