These demos present an in-depth view of various front
end design products relative to Analog/RF/Mixed Signals.
Scroll down to view all demos or select a vendor name
from either menu.
MQA (SPICE Model Quality Assurance) Demo
Model Quality Assurance (MQA) automatically assesses the quality of foundry-supplied models, generates the documentation,
and compares multiple model libraries, versions, and SPICE platforms. Model Builder Program (MBP) generates and optimizes
SPICE models using data from silicon wafer testing.
Microwave Office
Microwave Office, is the design suite that revolutionized product development by shifting the balance of power
back into the hands of high frequency design engineers. This demo shows how Microwave Office provides everything
designers need to take an idea from concept through simulation and directly into physical implementation.
Visual System Simulator™
Visual System Simulator is a comprehensive design suite for end-to-end communications systems. The VSS technology
uses a complex envelope simulation engine that enables systems and circuit designers to work together within
a common simulation framework to perform interactive, top-down analysis of analog and digital communications
systems and RF sub-systems.
AWR SI™ Design Suite
The AWR SI Design Suite combines the unique AWR design platform and
unified data model with a signal integrity analysis environment, providing comprehensive, easy-to-use analysis capabilities that work
seamlessly in one integrated platform. The solution supports multiple process technologies, enabling concurrent design and signal
integrity analysis of complex interconnects spanning chip, package, module, and PCB design boundaries.
Analog Office Analog and RFIC Design Suite
Analog Office is the first complete IC design system in over ten years that is specifically architected and
optimized from the ground up for next generation analog and RFIC designs. The solution, which is focused on
total RF closure, boasts an industry-first, concurrent interconnect-driven and RF-aware design methodology
in a unified design environment that delivers unprecedented ease-of-use, interactivity and openness.
Advanced Virtuoso Design Environment (IC 6.1 release)
This demo focuses on the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment.
You will discover some of the new features and functionality that are available, focusing on the enhanced productivity that
designers enjoy with the introduction of assistance. You will also learn about the constraint management system that can be
used to pass information the schematic through to layout.
NOTE: This demo requires 1280 x 1024 Minimum Screen Resolution and a Minimum 400 Kbps network connection.
In addition, a faster computer (1Ghz+, 512K RAM) is recommended for optimal playback.
Accelerated Physical Design with Virtuoso Prototype Flow (IC 6.1 release)
Discover the new, common cockpit that integrates all the Virtuoso products designers can access at any point and time during the design. You will see how to quickly perform area estimation on a piece of data, obtain the information, and plug it into a floor planning technology. You will also see simple editing to correct violations, the use of pin placement technology, and design optimization.
Virtuoso Constraint Flow (IC 6.1 release)
Explore how constraints can help designers manage their design environment. The demo will take you from design schematic into layout, and then into routing – all in one, easy-to-use design cockpit.
Solving D/MS Design Challenges with Virtuoso AMS Designer
Discover how you can effectively design mixed-signal chips, regardless of design size. Virtuoso AMS Designer
is the latest technological break through that brings the power of behavioral modeling to the IC designer.
It tackles the difficult challenge of converging massive digital designs with precise analog circuitry and simulating
them accurately and quickly, while using Verilog-AMS/VHDL-AMS languages, Virtuoso Schematic Editor schematics, Assura™
extracted views, timing views from SoC Encounter, and textual descriptions for NC-Sim. (This demo features custom design products from IC 5.1.41 release).
PyCell Studio™ & PCell Xtreme™ While interoperability has progressed rapidly in the digital domain, analog design has lagged behind, due in part to the lack of an interoperable PCell mechanism. This has made interoperability between multiple vendors' tools difficult. PyCell Studio helps designers reduce the time and cost of PCell and layout generator creation for deep submicron processes. PCell Xtreme enables the migration of PCells created in proprietary languages into multi-vendor OpenAccess flows. Together, PyCell Studio and PCell Xtreme provide a complete, interoperable OpenAccess PCell solution. Download PyCell Studio for free at www.ciranova.com. (video available to all Demos on Demand members)
Streamlining Design Team Collaboration with ClioSoft DM Solutions
ClioSoft is a leading provider of design data management solutions for the electronics design industry.
The multi-site development environment and cross-platform support enables global team collaboration and efficient management of design data and processes
from concept to tape-out. ClioSoft's SOS Data Collaboration Platform is integrated with EDA tools from leading vendors and provides seamless data
management solutions for RTL, Cadence® IC, and Mentor Graphics® IC design flows.
SystemView by Elanix
SystemView by Elanix is used to design, model and simulate a complete BER analysis of a QPSK system with encoded pulse shaped
signals — and to evaluate system performance by tuning components (such as filters and RF amplifiers) to fit design specifications.
Expedition Series
Many designers are facing barriers to successful PCB design caused by rapidly advancing PCB, IC, FPGA and
packaging technologies. If you don't have the right design solution, these barriers can prevent you from
completing your designs on time and within budget. Learn how to address these challenges using the Expedition
Series, Mentor Graphics’ complete PCB design solution for the creation of today's most complex PCB designs.
Challenges and Solutions for Verification of Post-Layout Nanometer Designs
Simon Young, Product Line Director To lower cost and improve the chances of silicon
success, IC's manufactured in 130 nanometer processes
and below must analyze the effects that can prevent
design success. Drivers for using nanometer processes,
and the challenges for verification are discussed in
this presentation. Topics include reliability of power
and signal networks; the timing impact of dynamic voltage
drop in power networks; dynamic crosstalk noise due
to coupling capacitance; and MOSFET device reliability.
Unleash the Power of Simulation - SPICE Explorer Sandwork Design’s netlist debugging and universal waveform analysis tools greatly enhance
design flows incorporating analog or mixed signal simulators from major vendors including Cadence, Synopsys, Nassda,
Mentor Graphics.
Synopsys Discovery AMS - COMING SOON!
Discovery AMS is Synopsys' mixed-signal verification
solution based on industry leading golden simulators
VCS, NanoSim and HSPICE. These simulators are best-in-class
stand alone tools, and when unified in a common environment
provide a unique combination of accuracy, performance,
and capacity with the flexibility of simulating design
abstractions in any combination of Verilog, SPICE, Verilog-A
and Verilog-AMS.
HiPer Silicon™ for Analog/Mixed Signal IC Design
See Tanner EDA’s HiPer Silicon™ in action – a complete IC design suite consisting of tools for schematic capture,
circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. Learn how HiPer Silicon can help you increase productivity and
speed your design concept to silicon.
GoldenGate Simulator
This in-depth demo shows how Xpedion’s GoldenGate RF
Simulator enables advance RF simulation and analysis
with high accuracy, robust convergence and rapid runtimes
in the Cadence ADE design flow.
