These demos present an in-depth view of various front end design products relative to behavioral simulation. Scroll down to view all demos or select a vendor name from either menu.
 
Aldec ARM ChipVision Design Systems CoFluent Design Eagleware-Elanix Mirabilis Design
Active-HDL: A complete FPGA Design Entry and Verification Environment
Active-HDL is the leading design entry and simulation environment for all FPGA and CPLD device families. It provides the flexibility and advanced features to support today's most complex designs for VHDL, Verilog, C/C++
and EDIF simulation from a single design entry and verification environment.

     
 
AMBA 3 AXI The Protocol Advantage
David Ptak, Synopsys
Today’s technical and market pressures drove the creation of the AMBA® 3 AXI™ protocol, which is designed to enable implementation of a high performance scalable bus interconnect architecture. This session begins with a short intro to the AMBA 3 AXI protocol followed by a deep technical session explaining the protocol itself and how it enables high-performance, high-bandwidth, low-latency bus interconnect operation. The presentation leverages the DesignWare Verification IP to introduce the protocol and provides insight into jump starting your own AMBA 3 AXI design verification tasks.

     
 
Synopsys/ARM Verification Methodology
Ramnath N. Rao, Synopsys
The Verification Methodology Manual (VMM) for SystemVerilog is an open verification methodology and library based on Synopsys’ proven Reference Verification Methodology. This session provides insight into the VMM methodology and how it helps maximize design quality, promote reuse among components, and emphasizes a layered, coverage driven, constrained random verification environment. The session documents the layered architecture, verification flow and transaction channel objects as defined by the Verification Methodology Manual for SystemVerilog.

     
 
DesignWare VIP Detailed Usage
Darrin Mossor, Synopsys
The Synopsys DesignWare Verification IP for AMBA 3 AXI provides an effective method of verifying AMBA 3 AXI protocol based designs. This session provides in-depth technical insight into working with the Verification Methodology Manual for SystemVerilog compliant and “AMBA 3 Assured” DesignWare Verification IP. The DesignWare Verification IP for AMBA 3 AXI includes master, slave, monitor and verification interconnect components with each supporting all the AMBA 3 AXI address, data widths, and protocol transfer and response types. The session documents how this full featured command set can be utilized to create both a directed test transaction environment as well as how to leverage the coverage driven, constrained random verification interface support.

     
 
ChipVision ORINOCO® - From Algorithm to Low-power Implementation
This in-depth demo shows how ORINOCO enables you to define the low-power optimized micro architecture for data-flow dominated blocks in SoCs. Starting from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro architecture of a block for implementation and guides your optimization of the number of algorithmic resources, memory accesses and allocations, resulting in the best low-power architecture.

     
 
CoFluent Studio™
CoFluent Studio™ is a visual Electronic System-Level (ESL) architectural development solution that enables performance analysis of complex hardware/software systems through a unique mapping technology. From simple graphics and C code, users create timed-behavioral application models that are devoid of implementation detail. Then, platform modeling is done independently by graphically assembling generic performance models of hardware components. Finally, following a Y design flow, application and platform models are merged through a simple drag-and-drop mapping operation to obtain an architectural model of the complete hardware / software system. CoFluent Studio automatically generates SystemC code from the graphical timed-behavioral or architectural descriptions.

     
 
SystemView by Elanix
SystemView by Elanix is used to design, model and simulate a complete BER analysis of a QPSK system with encoded pulse shaped signals — and to evaluate system performance by tuning components (such as filters and RF amplifiers) to fit design specifications.

     
 
VisualSim™ - System-level Performance Analysis and Architecture Design
VisualSim™ Architect is used for conceptual exploration, performance analysis and architecture design of electronics and embedded systems. The pre-defined, parameterized library blocks and multi-domain simulation kernel enables engineers to design the digital, IC, embedded software, image processing, analog, DSP and control systems. The advantages of using VisualSim Architect are to create large models quickly, execute faster system simulations and standardize communications through visual specifications.

     
     
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