Active-HDL: A complete
FPGA Design Entry and Verification Environment
Active-HDL is the leading design entry and simulation environment for all FPGA and CPLD device families.
It provides the flexibility and advanced features to support today's most complex designs for VHDL,
Verilog, C/C++ and EDIF simulation from a single design entry and verification environment.
EASI Tools Suite
The Beach Solutions EASI Tools Suite is a sophisticated set of integrated EDA tools that manage and auto-generate registers and register-related deliverables to accelerate the development of SoC designs.
Graphical RTL design with VRTL
This demo illustrates the benefits, features, and use of VRTL for rapid front-end RTL design. VRTL is a graphical
design-entry tool capable of generating synthesizable Verilog RTL code from logic block schematics.
Included is a demonstration of a FIFO being implemented with VRTL.
HiPer Silicon for Analog/Mixed Signal IC Design
See Tanner EDA’s HiPer Silicon in action – a complete IC design suite consisting of tools for schematic capture,
circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. Learn how HiPer Silicon can help you increase productivity and
speed your design concept to silicon.