CATEGORIES
Floor Planning Design Analysis
FLOOR PLANNING
Accelicon Cadence ChipVision Design Systems Silicon Dimensions
MQA (SPICE Model Quality Assurance) Demo
Model Quality Assurance (MQA) automatically assesses the quality of foundry-supplied models, generates the documentation, and compares multiple model libraries, versions, and SPICE platforms. Model Builder Program (MBP) generates and optimizes SPICE models using data from silicon wafer testing.

     
 
Encounter Platform Overview - the Route to Big, Fast Chips
Cadence Encounter™ digital IC design platform employs a continuous convergence methodology that will get you to wires fast. It combines silicon virtual prototyping and detailed IC implementation into a unified system with a single in-memory data model and user interface. Encounter provides the route to bigger, faster chips so that you can get more out of your silicon.

     
 
ChipVision ORINOCO® - From Algorithm to Low-power Implementation
This in-depth demo shows how ORINOCO enables you to define the low-power optimized micro architecture for data-flow dominated blocks in SoCs. Starting from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro architecture of a block for implementation and guides your optimization of the number of algorithmic resources, memory accesses and allocations, resulting in the best low-power architecture.

     
 
 
Chip2Nite™
The Chip2Nite platform gives logic designers the necessary tools and methodologies to perform early design planning and analysis before hand-off to the physical design team. The platform is available in various suites targeted at identifying and solving design closure issues. By providing logic designers with access to vital information they never readily had, critical design errors can be identified and resolved quickly eliminating costly iterations from logic to physical design.
 
     
DESIGN ANALYSIS DEMOS
Eagleware-Elanix GigaScale IC Silicon Dimensions
 
SystemView by Elanix
SystemView by Elanix is used to design, model and simulate a complete BER analysis of a QPSK system with encoded pulse shaped signals — and to evaluate system performance by tuning components (such as filters and RF amplifiers) to fit design specifications.

 
 
InCyte®
InCyte® is a revolutionary new specification optimization system that dramatically reduces the risk, design time and cost of IC design. It accurately estimates key IC specifications including; size, power, leakage, speed, cost, and yield.

 
 
Chip2Nite™
The Chip2Nite platform gives logic designers the necessary tools and methodologies to perform early design planning and analysis before hand-off to the physical design team. The platform is available in various suites targeted at identifying and solving design closure issues. By providing logic designers with access to vital information they never readily had, critical design errors can be identified and resolved quickly eliminating costly iterations from logic to physical design.
 
 
     
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