These demos present an in-depth view of various front end design products
relative to ESL / architectural design. Scroll down to view all demos or select
a vendor name from either menu.
EASI Tools Suite
The Beach Solutions EASI Tools Suite is a sophisticated set of integrated EDA tools that manage and auto-generate registers and register-related deliverables to accelerate the development of SoC designs.
Bluespec Technical Overview
The Bluespec toolset, the only ESL synthesis solution for control logic and
complex datapaths, significantly accelerates hardware design and reduces
verification costs. Bluespec presents hardware designers an exciting new way to
implement a design with correct-by-construction control logic synthesis while
retaining full control over the architecture and performance of the design.
This technical overview provides a review of the toolset, examples, technology
and key benefits.
ChipVision ORINOCO® - From Algorithm to Low-power Implementation
This in-depth demo shows how ORINOCO enables you to define the low-power
optimized micro architecture for data-flow dominated blocks in SoCs. Starting
from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro
architecture of a block for implementation and guides your optimization of the
number of algorithmic resources, memory accesses and allocations, resulting in
the best low-power architecture.
CoFluent Studio™
CoFluent Studio™ is a visual Electronic System-Level (ESL) architectural development solution that enables performance analysis of complex hardware/software systems through a unique mapping technology. From simple graphics and C code, users create timed-behavioral application models that are devoid of implementation detail. Then, platform modeling is done independently by graphically assembling generic performance models of hardware components. Finally, following a Y design flow, application and platform models are merged through a simple drag-and-drop mapping operation to obtain an architectural model of the complete hardware / software system. CoFluent Studio automatically generates SystemC code from the graphical timed-behavioral or architectural descriptions.
CoWare Platform Architecture Design Solution
CoWare's Platform Architecture Design Solution focuses on the challenges associated with the optimization and performance validation of the backbone interconnect and global memory subsystem of the SoC. Architects are looking to ESL methods to greatly improve the analysis and decision making process. They know RTL methods are too slow and lack the visibility needed to analyze design performance, configure complex on-chip interconnect, and optimize the global memory hierarchy. The results are over-design, cost increases, schedule delays, and re-spins. CoWare's Platform Architecture Design Solution provides our customers with production proven ESL technology and methodology to measurably improve their product performance and cost while reducing their design cycle time by 50% vs. traditional RTL methods.
SystemView by Elanix
SystemView by Elanix is used to design, model and simulate a complete BER
analysis of a QPSK system with encoded pulse shaped signals — and to evaluate
system performance by tuning components (such as filters and RF amplifiers) to
fit design specifications.
VisualSim™ - System-level Performance Analysis and Architecture Design
VisualSim� Architect is used for conceptual exploration, performance analysis
and architecture design of electronics and embedded systems. The pre-defined,
parameterized library blocks and multi-domain simulation kernel enables
engineers to design the digital, IC, embedded software, image processing,
analog, DSP and control systems. The advantages of using VisualSim Architect
are to create large models quickly, execute faster system simulations and
standardize communications through visual specifications.
SpiraTech Cohesive� Product Line This in-depth demo shows how the Cohesive� suite addresses the problem of full spectrum
abstraction adaptation and the lack of real connectivity between ESL and RTL. You'll see how, during the adaptation
process, the Cohesive� products are able to capture and visualize activity at the transaction levels and
simultaneously relate that activity to individual wires and signals in an RTL environment.
Synfora PICO Express Demo PICO Express is a potent combination of configurable IP and exploration and configuration
tools that explores and builds RTL directly from algorithm C descriptions. PICO Express takes algorithm descriptions
expressed in terms of sequences of nested loops and maps this to a highly optimized pipeline processor array
(PPA) architecture. PICO Express supports multiple loops with streaming data and creates a single, rate matched
RTL block. PICO Express provides extensive verification and integration capabilities to ensure that verification
and integration is minimized along with RTL creation.
Early SW Development using Synopsys Virtual Platforms Virtual Platforms are software models of complete systems that accelerate software development and hardware/software integration before hardware is available. During this demo you will learn how a Virtual Platform of your target improves software development productivity, typically by a factor of 2-5x. Synopsys is the leader in Virtual Platform technology, based on an unmatched track record of more than 40 of the most complex Virtual Platforms actively deployed with customers.
True DSP Synthesis This whiteboard discussion introduces the concept of True DSP synthesis and how it is different from other methods of
going from DSP algorithm to RTL code for hardware implementation. This discussion covers
topics including design languages, the importance of a technology-independent flow, and
automatic application of DSP synthesis optimizations.
XPRES Compiler Demo
Tensilica's XPRES compiler enables rapid development of optimized SoC devices.
Designers enter their algorithms directly in C or C++ and compiles these into
an optimized, pre-verified RTL description of an Xtensa LX processor core.
