EASI Tools Suite
The Beach Solutions EASI Tools Suite is a sophisticated set of integrated EDA tools that manage and auto-generate registers and register-related deliverables to accelerate the development of SoC designs.
Bluespec Technical Overview
The Bluespec toolset, the only ESL synthesis solution for control logic and
complex datapaths, significantly accelerates hardware design and reduces
verification costs. Bluespec presents hardware designers an exciting new way to
implement a design with correct-by-construction control logic synthesis while
retaining full control over the architecture and performance of the design.
This technical overview provides a review of the toolset, examples, technology
and key benefits.
Metric Driven Verification 101
You can not improve what you can not measure. Learn how to implement a metric driven verification environment to improve predictability, productivity, and quality of your chip development.
Next-generation High Level Synthesis: Cadence C-to-Silicon Compiler
Cadence C-to-Silicon Compiler (CtoS) is next-generation high-level synthesis technology for automating SoC IP development and reuse. Using embedded logic synthesis, CtoS automatically generates synthesizable RTL and/or technology-mapped gates for both datapath and control functions, starting from timed and untimed C/C++/SystemC(r) algorithm descriptions. Using CtoS, designers can reduce engineering effort by up to 90%, while achieving quality of results at or above whatever is possible using best manual RTL coding practices.
ChipVision ORINOCO® - From Algorithm to Low-power Implementation
This in-depth demo shows how ORINOCO enables you to define the low-power
optimized micro architecture for data-flow dominated blocks in SoCs. Starting
from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro
architecture of a block for implementation and guides your optimization of the
number of algorithmic resources, memory accesses and allocations, resulting in
the best low-power architecture.
CoFluent Studio™ is a visual Electronic System-Level (ESL) architectural development solution that enables performance analysis of complex hardware/software systems through a unique mapping technology. From simple graphics and C code, users create timed-behavioral application models that are devoid of implementation detail. Then, platform modeling is done independently by graphically assembling generic performance models of hardware components. Finally, following a Y design flow, application and platform models are merged through a simple drag-and-drop mapping operation to obtain an architectural model of the complete hardware / software system. CoFluent Studio automatically generates SystemC code from the graphical timed-behavioral or architectural descriptions.
SystemView by Elanix
SystemView by Elanix is used to design, model and simulate a complete BER
analysis of a QPSK system with encoded pulse shaped signals — and to evaluate
system performance by tuning components (such as filters and RF amplifiers) to
fit design specifications.
VisualSim™ - System-level Performance Analysis and Architecture Design
VisualSim� Architect is used for conceptual exploration, performance analysis
and architecture design of electronics and embedded systems. The pre-defined,
parameterized library blocks and multi-domain simulation kernel enables
engineers to design the digital, IC, embedded software, image processing,
analog, DSP and control systems. The advantages of using VisualSim Architect
are to create large models quickly, execute faster system simulations and
standardize communications through visual specifications.
SpiraTech Cohesive� Product Line This in-depth demo shows how the Cohesive� suite addresses the problem of full spectrum
abstraction adaptation and the lack of real connectivity between ESL and RTL. You'll see how, during the adaptation
process, the Cohesive� products are able to capture and visualize activity at the transaction levels and
simultaneously relate that activity to individual wires and signals in an RTL environment.
XPRES Compiler Demo
Tensilica's XPRES compiler enables rapid development of optimized SoC devices.
Designers enter their algorithms directly in C or C++ and compiles these into
an optimized, pre-verified RTL description of an Xtensa LX processor core.