CATEGORIES
TB Generation Design Analysis HW/SW CoDesign/Verification
Simulation Formal Tools Debug Tools
Emulation Acceleration Verification IP
TB GENERATION DEMOS
ARM Cadence Spiratech
 
Synopsys/ARM Verification Methodology
Ramnath N. Rao, Synopsys
The Verification Methodology Manual (VMM) for SystemVerilog is an open verification methodology and library based on Synopsys’ proven Reference Verification Methodology. This session provides insight into the VMM methodology and how it helps maximize design quality, promote reuse among components, and emphasizes a layered, coverage driven, constrained random verification environment. The session documents the layered architecture, verification flow and transaction channel objects as defined by the Verification Methodology Manual for SystemVerilog.
     
 
Incisive Plan-to-Closure Methodology for SystemVerilog
The Incisive Plan-to-Closure Methodology for SystemVerilog demo details the Cadence SystemVerilog solution. After introducing how Cadence has stitched SystemVerilog into its broad verification solution, the demo shows unique technical advantages and code examples that describe how to build SystemVerilog Universal Verification Components (UVCs). The UVCs created in the demo are shown operating in a verification environment. The demo concludes with information on additional resources available to the viewer.
     
 
SpiraTech Cohesive™ Product Line
This in-depth demo shows how the Cohesive™ suite addresses the problem of full spectrum abstraction adaptation and the lack of real connectivity between ESL and RTL. You'll see how, during the adaptation process, the Cohesive™ products are able to capture and visualize activity at the transaction levels and simultaneously relate that activity to individual wires and signals in an RTL environment.
 
 
     
SIMULATION DEMOS
Aldec ARM Cadence Fintronic Verisity
 
Active-HDL: A complete FPGA Design Entry and Verification Environment
Active-HDL is the leading design entry and simulation environment for all FPGA and CPLD device families. It provides the flexibility and advanced features to support today's most complex designs for VHDL, Verilog, C/C++
and EDIF simulation from a single design entry and verification environment.
     
 
AMBA 3 AXI The Protocol Advantage
David Ptak, Synopsys
Today’s technical and market pressures drove the creation of the AMBA® 3 AXI™ protocol, which is designed to enable implementation of a high performance scalable bus interconnect architecture. This session begins with a short intro to the AMBA 3 AXI protocol followed by a deep technical session explaining the protocol itself and how it enables high-performance, high-bandwidth, low-latency bus interconnect operation. The presentation leverages the DesignWare Verification IP to introduce the protocol and provides insight into jump starting your own AMBA 3 AXI design verification tasks.
     
 
Synopsys/ARM Verification Methodology
Ramnath N. Rao, Synopsys
The Verification Methodology Manual (VMM) for SystemVerilog is an open verification methodology and library based on Synopsys’ proven Reference Verification Methodology. This session provides insight into the VMM methodology and how it helps maximize design quality, promote reuse among components, and emphasizes a layered, coverage driven, constrained random verification environment. The session documents the layered architecture, verification flow and transaction channel objects as defined by the Verification Methodology Manual for SystemVerilog.
     
 
Solving D/MS Design Challenges with Virtuoso AMS Designer
Discover how you can effectively design mixed-signal chips, regardless of design size. Virtuoso AMS Designer is the latest technological break through that brings the power of behavioral modeling to the IC designer. It tackles the difficult challenge of converging massive digital designs with precise analog circuitry and simulating them accurately and quickly, while using Verilog-AMS/VHDL-AMS languages, Virtuoso Schematic Editor schematics, Assura™ extracted views, timing views from SoC Encounter, and textual descriptions for NC-Sim. (This demo features custom design products from IC 5.1.41 release).
 
     
 
Fintronic FinSim Demonstration
This in-depth demo tours Super-FinSim's OVI-compliant Verilog compiler, simulation builder, simulation kernel, and the GUI that drives them. Fintronic's simulator has established itself as the primary simulator to fit this paradigm because of its low memory utilization and its support for 64-bit architectures which allow it to simulate even the largest circuits on a single computer.
 
     
 
SpeXsim
This in-depth demo tours SpeXsim™, Verisity's integration of our flagship Specman Elite® with our third-generation Xsim® simulator. This package enables the mainstream engineering community to adopt Verisity's world-class technology. SpeXsim is offers high performance, out-of-the-box interoperability and ease of installation.
 
 
     
EMULATION DEMOS
Cadence EVE Engineering Synplicity
 
Cadence Palladium II Accelerator/Emulator Demo
George Zafiropoulos, Ken Mason, Philip deBuren
As part of the Incisive™ verification platform, Palladium II delivers high performance hardware acceleration and in-circuit emulation. This demonstration shows how to increase your simulation performance by using three different simulation acceleration use models (signal-based acceleration, transaction-based acceleration and embedded-testbench acceleration). It also shows how you can port your embedded assertions into Palladium II. In addition, we will show you how Palladium II can get up to 10,000x performance gain and provide full system verification through in-circuit emulation. Lastly, you will learn how to connect Palladium II to a real-world environment that is running at full speed, leveraging Cadence SpeedBridge solutions.
 
     
 
Booting and Debugging Linux in Emulation with ZeBu
Can you cycle-accurately boot a complete operating system and debug concurrently at the hardware and software level? With ZeBu, a hardware-assisted verification platform, you can. This demo walks you through a few HW/SW bugs encountered during the boot of a Linux kernel and web browser application software, and shows how bugs in hardware and software can be isolated, reproduced and fixed faster than ever before.
 
     
 
ZeBu: The Fastest Verification
ZeBu is an advanced hardware-assisted verification platform that combines the best aspects of traditional emulation and rapid prototyping systems into a single, unified environment for both ASIC/SoC debugging and embedded software validation. With the high capacity, easy setup and debugging associated with emulation, and the price/ performance of rapid prototyping, EVE enables both hardware designers and software developers to collaborate on a common design representation.
 
     
 
Synplicity Certify® ASIC RTL Prototyping Software
This video demonstrates the Certify® solution, a tool for creating ASIC prototypes implemented in FPGAs, in a three-step process - compiling the design, partitioning the design, and mapping out the FPGAs specified.
 
 
     
 
TotalRecall™ Full Visibility Technology
This whiteboard demonstrates the revolutionary new TotalRecall technology which enables you to debug and verify ASIC/SOC designs, ASSPs, and FPGAs at real hardware speed with full signal and state visibility.
 
 
     
DESIGN ANALYSIS DEMOS
ChipVision Design Systems Sequence TransEDA
ChipVision ORINOCO® - From Algorithm to Low-power Implementation
This in-depth demo shows how ORINOCO enables you to define the low-power optimized micro architecture for data-flow dominated blocks in SoCs. Starting from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro architecture of a block for implementation and guides your optimization of the number of algorithmic resources, memory accesses and allocations, resulting in the best low-power architecture.
     
 
POWERTHEATER - Power Management And Low-Power Design
Power Management And Low-Power Design Take a seat, have some popcorn, relax, and watch PowerTheater's unparalleled low-power RTL design and analysis capabilities bring the screen to life. Two thumbs up for its ability to easily fit into mainstream flows (including the new Novas FSDB interface) while providing design teams with the means to tame power consumption.
 
     
 
imPROVE-HPK Hardware Protocol Verification
imPROVE-HPK is a formal verification tool dedicated to the verification of hardware designs based on standard protocol interfaces (OCP, Amba AHB, etc). imPROVE-HPK is fully automatic and very easy to set-up and use in any design and verification environment. The tool automatically creates a complete protocol environment for the design, and then subsequently checks each of the protocol properties (including functional performance analysis properties) and coverage scenarios.
 
 
     
FORMAL TOOLS DEMOS
0-IN AXIOM Cadence Calypto TransEDA
 
0-IN Assertion-Based Verification Suite
This demo presents the capabilities of 0-In's Assertion-Based Verification (ABV) Suite, the most complete ABV solution available for finding more bugs faster in SoC and ASIC designs.
 
     
 
@Verifier
The @Verifier suite is the most comprehensive assertion-based verification product available, supporting both PSL and SystemVerilog. As this demo shows, the suite includes @Verifier-DP for distributed processing on existing server farms, and @Verifier-ZX, adding the powerful formal solvers based on IBM RuleBase technology.
 
     
 
Formal ABV using Incisive Formal Verifier (IFV)
Improve verification productivity with formal-assertion verification that provides easy adoption, ease-of-use, and broad assertion support including SystemVerilog assertions, PSL, OVL, and the Incisive Assertion Library.
 
     
 
SLEC™: The Industry’s First Sequential Equivalence Checker
As the industry’s first sequential equivalence checker, SLEC can verify block-level designs with differences in sequential and data abstraction. SLEC provides comprehensive functional verification for designers doing micro-architectural RTL optimization, such as re-timing, pipelining, and resource sharing, and engineering teams deploying system-level design flows including those using behavioral synthesis.
 
     
 
VN-Cover Coverability Analysis Option
Coverability Analysis, an option to TransEDA's VN-Cover coverage analysis tool, guides designers on the shortest path to full coverage, filtering out unreachable design parts while enabling users to check if the uncovered branches are reachable or not. Coverability Analysis is fully integrated into VN-Cover, running automatically either on all remaining uncovered branches or on specific ones selected by the user via the GUI.
 
 
     
ACCELERATION DEMOS
Cadence EVE Engineering Synplicity Tharas
 
Cadence Palladium II Accelerator/Emulator Demo
George Zafiropoulos, Ken Mason, Philip deBuren
As part of the Incisive™ verification platform, Palladium II delivers high performance hardware acceleration and in-circuit emulation. This demonstration shows how to increase your simulation performance by using three different simulation acceleration use models (signal-based acceleration, transaction-based acceleration and embedded-testbench acceleration). It also shows how you can port your embedded assertions into Palladium II. In addition, we will show you how Palladium II can get up to 10,000x performance gain and provide full system verification through in-circuit emulation. Lastly, you will learn how to connect Palladium II to a real-world environment that is running at full speed, leveraging Cadence SpeedBridge solutions.
 
     
 
Booting and Debugging Linux in Emulation with ZeBu
Can you cycle-accurately boot a complete operating system and debug concurrently at the hardware and software level? With ZeBu, a hardware-assisted verification platform, you can. This demo walks you through a few HW/SW bugs encountered during the boot of a Linux kernel and web browser application software, and shows how bugs in hardware and software can be isolated, reproduced and fixed faster than ever before.
 
     
 
ZeBu: The Fastest Verification
ZeBu is an advanced hardware-assisted verification platform that combines the best aspects of traditional emulation and rapid prototyping systems into a single, unified environment for both ASIC/SoC debugging and embedded software validation. With the high capacity, easy setup and debugging associated with emulation, and the price/ performance of rapid prototyping, EVE enables both hardware designers and software developers to collaborate on a common design representation.
 
     
 
The HAPS Concept
HAPS is a modular board system that provides real-time speed, real-time debugging and full ASIC functionality for ASIC prototype designers. The system is composed of stackable multi-FPGA mother boards and one or more standard or custom-made daughter boards. Using HAPS, the ASIC prototype gives designers the same functionality and performance as the ASIC. This presentation describes the HAPS-50-series of mother boards in detail.
 
     
 
Simulation Acceleration with Hammer 100, Hammer SX and Hammer MX
Functional verification is still the bottleneck in today's chip design process. The new Hammer families for simulation acceleration and emulation deliver hundreds of kilohertz run time speeds, combined with the industry's fastest turn-around times without compromising debug visibility. And, we offer the best price/performance in the industry.
 
 
     
HW/SW CODESIGN/VERIFICATION DEMOS
Adveda Aldec Cadence Celoxica EVE Engineering Impulse Mirabilis Design Obsidian
 
Adveda Miss Univers Demo
Miss Univers is a complete HW/SW co-verification tool for multi-processor SOC architectures, offering extensive debug capabilities, fast simulation and emulation support. It includes an RTL simulator as well as a multi-core IDE with most fascinating debug features and configurable user-friendly graphical user interface.
 
     
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