These demos present an in-depth view of various front end design products relative to timing and power analysis. Scroll down to view all demos or select a vendor name from either menu.
 
Altos Cadence Chip Vision Golden Gate Tech Incentia Sequence
 
Liberate™ and Variety™: Ultra fast IP Characterization Solutions from Altos Design Automation
This demo provides an in depth look at Liberate™ and Variety™, a new generation of IP characterization products from Altos Design Automation Inc. Utilizing Altos' novel "inside view" approach, the demo shows how characterization can be sped up significantly yet still yield the same accuracy with better model quality that existing approaches. The demo also highlights the challenges of modeling process variation and how Variety enables the creation of statistical timing libraries in order to reduce design guard bands thereby enabling faster timing closure and lower power consumption.

 
     
 
High Speed PCB Design and Analysis
Allegro PCB SI, an integrated design and analysis environment, tackles the problems found in today’s high speed systems. See how to design and verify high speed serial links, high speed memory interfaces, and power delivery networks.

 
     
Cadence© Low-Power Solution
The industry's first complete solution integrates logic design, verification, and implementation technology—all enabled with the Si2 Common Power Format (CPF)—to improve productivity, reduce risk, and achieve optimal trade-offs among timing, power, and area.

     
 
ChipVision ORINOCO® - From Algorithm to Low-power Implementation
This in-depth demo shows how ORINOCO enables you to define the low-power optimized micro architecture for data-flow dominated blocks in SoCs. Starting from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro architecture of a block for implementation and guides your optimization of the number of algorithmic resources, memory accesses and allocations, resulting in the best low-power architecture.

     
 
Power Plan Gold™ and Power Optimize Gold™
Power Plan Gold (PPG) efficiently creates complex power grids with unique Parametric Templates™ technology, PPG natively supports multiple supplies, analyzes the power grid for IR drop and EM violations and automatically repairs the grid. Power Optimize Gold automatically reduces power consumption by 15 – 20% or more using a proprietary WiresFirst™ algorithm while maintaining timing, SI, and EM constraints.

 
     
 
Incentia TimeBench Environment
TimeCraft is the fastest gate-level full-chip static timing analyzer in market today. It contains industry leading features for nanometer designs, including location-based on-chip-variation, parallel multi-mode multi-corner timing analysis, and signal integrity analysis for crosstalk and noise.

 
 
Sequence Design-For-Power Flow
Attack the challenges of low power design holistically, from RTL to GDS. Manage and reduce power. Avoid power problems. The only comprehensive tool suite, with advantages for managers, for SoC architects and designers, and for the physical implementation team: Design for Power with Sequence.

 
     
     
     
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