Compliance Management System Automates Compliance Verification
Verifying protocol compliance is typically time consuming and requires extensive protcol expertise. This demo shows off Cadence's new Compliance Management System (CMS) that automates compliance verification. With CMS, you can reach 70+% functional coverage without writing a single test. We’ll show you how easy it is to apply CMS to your AMBA or PCI Express verification project and briefly overview Cadence's extensive Verification IP portfolio.
Global Route Environment technology for Cadence® Allegro® PCB design
Discover a new route to advanced PCB design and layout and learn how using intelligent automation can eliminate manual processes while preserving the designer's intent. This demo will highlight the new Global Route Environment technology for Cadence® Allegro® PCB design. The Global Route Environment technology combines a graphical interconnect flow planning architecture and a hierarchically-aware global routing engine to provide PCB designers with an automated, intelligent planning and routing environment. This demo will highlight the new use model paradigm and how it solves ultra-complex PCB interconnect challenges where strategic planning and interconnect routing could previously only be done by manual methods.
High-performance Custom Routing and DFM Optimization for Advanced Process Nodes using the Cadence® Space-based Router and Chip Optimizer
View the all new innovative space-based gridless analysis driven routing and yield optimization solutions from Cadence Design Systems. The Cadence Space-based Router and Cadence Chip Optimizer deliver a silicon proven full-chip routing and DFM optimization solution that provide concurrent design and manufacturing convergence for improved design performance, manufacturability and yield at 65nm and below processes. The demo features the Cadence Space-based Router which is a custom IC high capacity, high performance convergent design routing solution for custom digital and analog mixed signal designs. The demo also features the Cadence Chip Optimizer, which is complimentary to the Cadence Space-based Router or any IC design routing solution for post-route model driven manufacturing and yield optimization.
Advanced Virtuoso Design Environment (IC 6.1 release)
This demo focuses on the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment.
You will discover some of the new features and functionality that are available, focusing on the enhanced productivity that designers enjoy with the introduction of assistance. You will also learn about the constraint management system that can be used to pass information the schematic through to layout.
NOTE: This demo requires 1280 x 1024 Minimum Screen Resolution and a Minimum 400 Kbps network connection. In addition, a faster computer (1Ghz+, 512K RAM) is recommended for optimal playback.
Accelerated Physical Design with Virtuoso Prototype Flow (IC 6.1 release)
Discover the new, common cockpit that integrates all the Virtuoso products designers can access at any point and time during the design. You will see how to quickly perform area estimation on a piece of data, obtain the information, and plug it into a floor planning technology. You will also see simple editing to correct violations, the use of pin placement technology, and design optimization.
Virtuoso Constraint Flow (IC 6.1 release)
Explore how constraints can help designers manage their design environment. The demo will take you from design schematic into layout, and then into routing all in one, easy-to-use design cockpit.
PyCell Studio™ & PCell Xtreme™
While interoperability has progressed rapidly in the digital domain, analog design has lagged, due in part to the lack of an interoperable PCell mechanism.
This has made interoperability between multiple vendors' tools difficult.
PyCell Studio helps reduce the time and cost of PCell and layout generator creation for deep submicron processes. PCell Xtreme enables the migration of
PCells created in proprietary languages into multi-vendor OpenAccess flows. Together, PyCell Studio and PCell Xtreme provide a complete, interoperable
OpenAccess PCell solution.
Download PyCell Studio for free at www.ciranova.com.
(This video is available to all Demos on Demand members, including vendors.)
Early SW Development using Synopsys Virtual Platforms
Virtual Platforms are software models of complete systems that accelerate software development and hardware/software integration before hardware is available. During this demo you will learn how a Virtual Platform of your target improves software development productivity, typically by a factor of 2-5x. Synopsys is the leader in Virtual Platform technology, based on an unmatched track record of more than 40 of the most complex Virtual Platforms actively deployed with customers.
HiPer Silicon for Analog/Mixed Signal IC Design
See Tanner EDAs HiPer Silicon in action a complete IC design suite consisting of tools for schematic capture,
circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. Learn how HiPer Silicon can help you increase productivity and
speed your design concept to silicon.
Diamond Standard Series Software Toolchain
This demo highlights the easy-to-use software development tools for Tensilicas Diamond Standard family of processor cores,
a set of six off-the-shelf synthesizable cores that range from area-efficient, low-power controllers to high-performance DSPs. The Diamond Standard Processor software development
tools include a complete compiler toolchain, instruction set simulator, performance analysis tools and project management tools.
High-Performance IC Design & Verification
This demo presents Nexxim, the state-of-the-art circuit simulator developed specifically to address the nonlinear and full-wave circuit behavior of high-performance RF/analog/mixed-signal ICs.
Nexxim works within established IC design flows to deliver rapid simulation speeds in the presence of large device counts and harmonic content all while retaining transistor level accuracy.
Bluespec Technical Overview
The Bluespec toolset, the only ESL synthesis solution for control logic and complex datapaths, significantly accelerates hardware design and
reduces verification costs. Bluespec presents hardware designers an exciting new way to implement a design with correct-by-construction
control logic synthesis while retaining full control over the architecture and performance of the design. This technical overview
provides a review of the toolset, examples, technology and key benefits.
ZeBu: The Fastest Verification
ZeBu is an advanced hardware-assisted verification platform that combines the best aspects of traditional emulation and rapid prototyping systems into a single,
unified environment for both ASIC/SoC debugging and embedded software validation. With the high capacity, easy setup and debugging associated with emulation,
and the price/ performance of rapid prototyping, EVE enables both hardware designers and software developers to collaborate on a common design representation.
Incentia TimeBench Environment
TimeCraft is the fastest gate-level full-chip static timing analyzer in market today.
It contains industry leading features for nanometer designs, including location-based on-chip-variation, parallel multi-mode multi-corner
timing analysis, and signal integrity analysis for crosstalk and noise.
Streamlining Design Team Collaboration with ClioSoft DM Solutions
ClioSoft is a leading provider of design data management solutions for the electronics design industry.
The multi-site development environment and cross-platform support enables global team collaboration and efficient management of design data and processes
from concept to tape-out. ClioSoft's SOS Data Collaboration Platform is integrated with EDA tools from leading vendors and provides seamless data
management solutions for RTL, Cadence® IC, and Mentor Graphics® IC design flows.
Designing Platform Based FPGAs Using Advanced Synthesis Tools
Complete easy-to-use RTL and physical synthesis environment offers new placement reuse and modular design flows,
along with expert-level optimization of challenging FPGA designs in all leading technologies for enhanced designer productivity.
Using Calibre to Implement DFM Analysis and Enhancement and Maximize Yield
Learn about how the Calibre Yield Analyzer and Calibre Yield Enhancer tools deliver a three-step approach to maximizing yield by:
1) Identifying the causes of design-to-process interactions and determining how these causes influence yield; 2) Analyzing where issues occur in the design and where these
issues can be corrected, enabling yield prediction; and 3) Making the necessary changes, both manually and automatically, that optimize yield.
Synplify® Premier Advanced FPGA Physical Synthesis and Debug
This video provides an overview of Synplicitys patented graph-based physical synthesis technology and introduces Synplify Premier software, the ultimate FPGA design and debug solution.
Reaching Power Closure with Apache's Physical Design Integrity Solutions
Power is one of the top concerns at 130 nanometer processes and below, especially for those used in low power applications.
In order to achieve optimal performance and yield for these designs, the integrity of the P/G design must be maintained.
This demo shows how Apache's RedHawk and PsiWinder analyze the impact of dynamic voltage drop on critical path timing and automatically fix and optimize P/G "hot spots."
Power Plan Gold and Power Optimize Gold
Power Plan Gold (PPG) efficiently creates complex power grids with unique Parametric Templates technology,
PPG natively supports multiple supplies, analyzes the power grid for IR drop and EM violations and automatically repairs the grid. Power Optimize Gold automatically
reduces power consumption by 15 20% or more using a proprietary WiresFirst algorithm while maintaining timing, SI, and EM constraints.
PureSpec verification IP is the leading solution for functional
verification of standard interfaces such as: PCI Express, USB, CE-ATA, SATA,
Ethernet, and ASI. Proven product quality, dedicated customer support, and
unmatched EDA and verification expertise make PureSpec the best-in-class
verification IP solution for all standard interfaces.
Debug System for Functional & System-Level Design & Physical Analysis
This demo shows how Novas cuts debug time in half throughout the entire design process from systems to RTL/Gate to silicon.
Starting with the Novas Verdi Debug System, youll learn how to quickly understand your design's behavior, automate the most time consuming aspects of debug,
and unify the environment including testbench analysis. You'll also see how our nESL product debugs system-level designs for embedded processor platforms and how
nAnalyzer allows debug and analysis of physical designs.