MQA (SPICE Model Quality Assurance) Demo
Model Quality Assurance (MQA) automatically assesses the quality of foundry-supplied models, generates the documentation,
and compares multiple model libraries, versions, and SPICE platforms. Model Builder Program (MBP) generates and optimizes
SPICE models using data from silicon wafer testing.
Active-HDL: A complete FPGA Design Entry and Verification Environment
Active-HDL is the leading design entry and simulation environment for all FPGA and CPLD device families. It provides the flexibility and
advanced features to support today's most complex designs for VHDL,
Verilog, C/C++ and EDIF simulation from a single design entry and verification environment.
Compex-RT Product Demo
Compex-RT is a space propagation tool for improving routability and/or achieve die size reduction. This demo will include Compex-RT's usable
space analysis, routability analysis, timing analysis, and space propagation for improved routability and die size reduction.
Blueview & Novas Debussy Demo: Source-Level Debugger for Bluespec's High-Level Synthesis
Cycle accurate C-based simulation with full Verilog
support provides both speed and debug visibility needed
to truly raise the level of design abstraction.
ChipVision ORINOCO® - From Algorithm to Low-power Implementation
This in-depth demo shows how ORINOCO enables you to define the low-power optimized micro architecture for data-flow dominated blocks in SoCs.
Starting from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro architecture of a block for implementation and guides your
optimization of the number of algorithmic resources, memory accesses and allocations, resulting in the best low-power architecture.
InCyte®
InCyte® is a revolutionary new specification optimization system that dramatically reduces the risk, design time
and cost of IC design. It accurately estimates key IC specifications including; size, power, leakage, speed,
cost, and yield.
CoDeveloper Demo
CoDeveloper provides C to RTL design and compilation for various
FPGA platforms including Xilinx and Altera. It enables you to create your own FPGA-based
custom platform and to target systems with external processors, including DSPs.
Manufacturing-IC Test
Personal Ocelot, allows Engineering teams to validate vectors, bring up and characterize first silicon
or to develop a test program. Conduct AC-Scan based Path and Transition Delay testing and capture memory to collect millions of bits of fail data logs for debug and diagnosis
of elusive problems. Modern BIST and SCAN design methodologies are well supported in hardware and software. Test programs developed on the Personal Ocelot may be
directly applied to the Ocelot production platform without changes—even in a Multi-Site configuration.
Interra Memory Development System
This in-depth demo shows how MC2 automates the design process for standard and embedded memories while also providing a platform for migration to new processes.
MC2 enhances the overall methodology for the design and distribution of memories to ensure the reuse of a base design over many generations of sub-micron processes.
Embedding ASICs in PLD
Lattice FPSCs pioneered the approach of putting ASIC embedded cores and FPGA
gates on the same silicon die. Unlike ASICs with FPGA gates, FPSCs have a
broad range of uses. The embedded cores hold industry standard IP, including
bus interface, high-speed line interface and high-speed transceiver cores.
When combined with programmable gates, FPSCs can be used in a variety of
advanced system designs. This demo shows a sample implementation of SPI 4.2
and configuration of the ASIC block using ispLEVER Development Tools.
VisualSim™ - System-level Performance Analysis & Architecture Design
VisualSim™ Architect is used for conceptual exploration, performance analysis and architecture design of electronics and embedded systems.
The pre-defined, parameterized library blocks and multi-domain simulation kernel enables engineers to design the digital, IC, embedded software, image processing, analog, DSP and control systems.
The advantages of using VisualSim Architect are to create large models quickly, execute faster system simulations and standardize communications through visual specifications.
VisualSim Architect provides a modeling and simulation approach to identify the best IP or component and implementation decision for a proposed functionality.
The advantage of VisualSim is to conduct these experiments at a higher level of abstraction, faster model construction and accelerate results generation.
VisualSim Architect aids HW/SW co-design, mapping of behavior to architecture, partitioning functions and to determine optimal resource sharing.
OPENCORES Open RISC demo
The Open RISC embedded processor platform shows both the features and full development platform available
from OpenCores. The open source, Open RISC 1200 processor is highlighted along with the complete GNU development
tool chain including a running applications and booting Linux.
Graphical RTL design with VRTL Demo
This demo illustrates the benefits, features, and use of VRTL for rapid front-end RTL design. VRTL is a graphical
design-entry tool capable of generating synthesizable Verilog RTL code from logic block schematics.
Included is a demonstration of a FIFO being implemented with VRTL.
ProTiming™ Demo
ProTiming™ is an add-on for Synopsys PrimeTime® that
automatically improves timing performance by an average of 10 percent by
intelligently selecting, placing, or combining standard cells, even in
designs previously optimized during the place-and-route flow.
Laker L Series
LAKER is a high productivity next generation custom layout tool. It contains the full-fledged traditional polygon editing features to provide the greatest flexibility and controllability, yet it offers many intelligent guidance and automation to make the layout creation,
editing tasks much more efficient and productive. With LAKER, users are able to complete the
layout designs and achieve the desired layout density and performance 2 to 6 times faster
than using other layout editors.
Tensilica XPRES Compiler
Tensilica's XPRES compiler enables rapid development of optimized SoC devices.
Designers enter their algorithms directly in C or C++ and compiles these into an optimized, pre-verified RTL description of an Xtensa LX processor core.
Empowering SOC Reuse with ViaMask and ViaPath
This demo provides a detailed tour of ViaMask™, an embeddable one-mask structured ASIC fabric that in conjunction with
ViaPath, an easy to use physical implementation software package, empowers you to reuse your valuable IP to serve multiple derivative applications.
Z Circuit Library Analyzer Demo
The Z Circuit Library Analyzer is a tool targeted towards
library integration engineers to help them with library tracking and analysis. It is
the first library analysis system that that gives you a thorough understanding of your
choices so that you can make the right decisions.
