Watch the EDA bigwigs answer your questions from ESNUG Post 452 about: the
Jasper rumors, why the Cadence Design Foundry failed, 0-in floundering,
the Synopsys vs. Magma lawsuit, SystemC adoption, System Verilog support,
the Freescale tool lock, the EDA price wars, DFM, Verisity, Forte,
Celoxica, and, of course, China and India.
Moderator: John Cooley
Panelists:
Rajeev Madhavan - CEO, Magma
Antun Domic - GM, Synopsys
Joe Sawicki - GM, Mentor Graphics
Ted Vucurevich - CTO, Cadence
Mike Giafagna - CEO, Aprio
Kathryn Karnen - CEO, Jasper DA
Brett Cline - The SystemC Poster Boy
Gary Smith - Gartner/Dataquest
FEATURED VERIFICATION DEMOS:
ZeBu: The Fastest Verification
ZeBu is an advanced hardware-assisted verification platform that combines the best aspects of traditional emulation and rapid prototyping systems into a single,
unified environment for both ASIC/SoC debugging and embedded software validation. With the high capacity, easy setup and debugging associated with emulation,
and the price/ performance of rapid prototyping, EVE enables both hardware designers and software developers to collaborate on a common design representation.
Cadence Palladium II Accelerator/Emulator Demo
Palladium II delivers high performance hardware acceleration and in-circuit
emulation. Learn how to increase your simulation performance by using three different simulation
acceleration use models (signal-based acceleration, transaction-based acceleration and embedded-testbench
acceleration). See how you can port your embedded assertions into Palladium II. Palladium II
can get up to 10,000x performance gain and provide full system verification through
in-circuit emulation. Lastly, learn how to connect Palladium II to a real-world environment
that is running at full speed, leveraging Cadence SpeedBridge solutions.
Tharas Accelerated Functional Verification Demo
Functional verification is the bottleneck in today's
chip design process. Tharas' Hammer hardware accelerator has a unique and cost-effective
approach whereby it offers a plug-n-play environment, with the industry's fastest
turn-around times without compromising debug visibility. And, we offer the best price/performance
in the industry.
Novas Debug System for Functional & System-Level Design & Physical Analysis
This demo shows how Novas cuts debug time in half throughout the entire design process from systems to RTL/Gate to silicon.
Starting with the Novas Verdi™ Debug System, you’ll learn how to quickly understand your design's behavior, automate the most time consuming aspects of debug,
and unify the environment including testbench analysis. You'll also see how our nESL product debugs system-level designs for embedded processor platforms and how
nAnalyzer allows debug and analysis of physical designs.
Formal ABV using Incisive Formal Verifier (IFV)
Improve verification productivity with formal-assertion verification that provides easy adoption,
ease-of-use, and broad assertion support including SystemVerilog assertions, PSL, OVL, and the Incisive Assertion Library.
SpeXsim
SpeXsim™, is Verisity's integration of their flagship Specman
Elite® with our third-generation Xsim® simulator. This combination enables the mainstream
engineering community to adopt Verisity's world-class technology. SpeXsim offers
high performance, out-of-the-box interoperability and ease of installation.
Adveda Miss Univers Demo
Miss Univers is a complete HW/SW co-verification tool for multi-processor SOC architectures,
offering extensive debug capabilities, fast simulation and emulation support. It includes an RTL simulator
as well as a multi-core IDE with most fascinating debug features and configurable user-friendly graphical user
interface.
@Verifier
The @Verifier suite is the most comprehensive assertion-based verification product available, supporting
both PSL and SystemVerilog. As this demo shows, the suite includes @Verifier-DP for distributed processing
on existing server farms, and @Verifier-ZX, adding the powerful formal solvers based on IBM RuleBase technology.
@DesignerPro
A next-generation graphical design and debugging
environment that provides assertion based verification as well as support for both
PSL and SystemVerilog assertions. @Designer-PRO works with VCS, NC-Sim / Incisive and ModelSim,
and is tightly integrated with our @Verifier formal model checking family.
DEMOS ON DEMAND™ on DeepChip
