See Tanner EDAs HiPer Silicon™ in action a complete IC design suite consisting of tools for schematic capture,
circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. Learn how HiPer Silicon can help you increase productivity and
speed your design concept to silicon.
This demo highlights the easy-to-use software development tools for Tensilicas Diamond Standard family of processor cores,
a set of six off-the-shelf synthesizable cores that range from area-efficient, low-power controllers to high-performance DSPs. The Diamond Standard Processor software development
tools include a complete compiler toolchain, instruction set simulator, performance analysis tools and project management tools.
The Bluespec toolset, the only ESL synthesis solution for control logic and complex datapaths, significantly accelerates hardware design and reduces verification costs.
Bluespec presents hardware designers an exciting new way to implement a design with correct-by-construction control logic synthesis while retaining full control over the architecture and
performance of the design.
ZeBu is an advanced hardware-assisted verification platform that combines the best aspects
of traditional emulation and rapid prototyping systems into a single, unified environment for both ASIC/SoC debugging and embedded software validation.
With the high capacity, easy setup and debugging associated with emulation, and the price/ performance of rapid prototyping,
EVE enables both hardware designers and software developers to collaborate on a common design representation.
TimeCraft is the fastest gate-level full-chip static timing analyzer in market today.
It contains industry leading features for nanometer designs, including location-based on-chip-variation, parallel multi-mode multi-corner
timing analysis, and signal integrity analysis for crosstalk and noise.
Streamlining Design Team Collaboration with ClioSoft DM Solutions
ClioSoft is a leading provider of design data management solutions for the electronics design industry.
The multi-site development environment and cross-platform support enables global team collaboration and efficient management of design data and processes
from concept to tape-out. ClioSoft's SOS Data Collaboration Platform is integrated with EDA tools from leading vendors and provides seamless data
management solutions for RTL, Cadence® IC, and Mentor Graphics® IC design flows.
Simulation Acceleration with Hammer 100, Hammer SX and Hammer MX
Functional verification is still the bottleneck in today's chip design process. The new Hammer families for simulation acceleration
and emulation deliver hundreds of kilohertz run time speeds, combined with the industry's fastest turn-around times without compromising debug visibility.
And, we offer the best price/performance in the industry.
Power Management and Power Grid Integrity in SoC Designs
Sequence solutions enable the SoC designers to minimize power consumption and create a robust power grid to minimize silicon risk.
PowerTheater's unparalleled low-power RTL design and analysis provides design teams with the means to tame power consumption.
CoolPower enables the designers to the minimize dynamic and leakage power consumption in the physical domain. CoolTime
enables the users to analyze and optimize the power grid for dynamic voltage drop issues for minimizing silicon risk.
Synplify® Premier Advanced FPGA Physical Synthesis and Debug
This video provides an overview of Synplicitys patented graph-based physical synthesis technology and introduces Synplify Premier software, the ultimate FPGA design and debug solution.
SLEC™: The Industrys First Sequential Equivalence Checker
As the industrys first sequential equivalence checker, SLEC can verify block-level designs with differences in sequential and data abstraction. SLEC provides
comprehensive functional verification for designers doing micro-architectural RTL optimization, such as re-timing, pipelining, and resource sharing, and engineering teams
deploying system-level design flows including those using behavioral synthesis.
