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Media Kit

SYNPLICITY

TotalRecall™ Full Visibility Technology
This whiteboard demonstrates the revolutionary new TotalRecall technology which enables you to debug and verify ASIC/SOC designs, ASSPs, and FPGAs at real hardware speed with full signal and state visibility.

ALTERA

Quartus II Software Overview
The Quartus® II software is the only design environment supporting FPGA, CPLD, and structured ASIC HardCopy™ device designs. This demo shows how to get started with Quartus II and highlights new software features.

IMPULSE

CoDeveloper Demo
CoDeveloper provides C to RTL design and compilation for various FPGA platforms including Xilinx and Altera.

SYNPLICITY

Identify® RTL Debugger
Identify allows FPGA and ASIC prototyping designers to debug their hardware directly in their RTL source code. This demo shows how Identify reduces hardware debug time by providing an easy and fast RTL-based debug environment.


To view demos in a specific category, review the classifications and make a selection.

ESL/Architectural Design

Software Development

Behavioral Simulation

Design Entry

Design Synthesis

Functional Verification

	TB Generation
	Simulation
	Emulation
	Design Analysis
	Formal Tools
	Acceleration
	HW/SW CoDesign/ Verification
	Debug Tools
	Verification IP

Analog/RF/Mixed Signal

Design Planning

	Floorplanning
	Design Analysis

Timing & Power Analysis

Design for Test (DFT)

	ATPG
	Scan Insertion





	Physical Design
	Physical Synthesis
	Extraction
	Post Layout Checks
	Physical Verification
	Circuit Simulation
	Design for Manufacturing



	Front End EDA
	Back End EDA
	SoC Development



	Frameworks
	Collaboration Tools
	Data Management
	Grid Computing



	Libraries
	Development Tools



	Packaging
	IC Test



	Structured ASIC
	Programmable

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