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| Category:
Front End - FV-HW/SW CoDesign/Verification |
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Miss Univers is a complete HW/SW co-verification
tool for multi-processor SOC architectures, offering extensive debug capabilities, fast
simulation and emulation support. It includes an RTL simulator as well as a multi-core
IDE with most fascinating debug features and configurable user-friendly graphical
user interface. |
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3/4/2005 - AdvEDA Adveda’s Univers multi-core Software IDE and HW/SW co-verification tool supports Altera’s Nios II Embedded Processor | 5/31/2004 - AdvEDA Adveda: SystemC model generator |
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