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Bluespec provides an industry standards-based EDA toolset that significantly raises the level of abstraction for ASIC and FPGA design while retaining the ability to automatically synthesize high quality RTL, without compromised speed, power or area.
   
Bluespec ESL Synthesis
Category: Front End - ESL/Architectural Design, Design Synthesis
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Technical Overview
The Bluespec toolset, the only ESL synthesis solution for control logic and complex datapaths, significantly accelerates hardware design and reduces verification costs. Bluespec presents hardware designers an exciting new way to implement a design with correct-by-construction control logic synthesis while retaining full control over the architecture and performance of the design.

Bluespec SystemVerilog Training
Presenter: Rishiyur Nikhil
This 12 session Bluespec SystemVerilog Training Course is the standard intro that Bluespec provides to their customers. Support resources for this training course including labs, downloadable PowerPoint slides, and documentation, are here.
Lectures 1 - 3
Lecture 1 is an Introduction. Lecture 2 covers Combinational Structures and Basic Types. Lecture 3 covers Types.
 
Lectures 4 - 6
Lecture 4 covers Module Hierarchy. Lecture 5 covers Rules. Lecture 6 covers Rule Scheduling.
 
Lectures 7 - 8
Lecture 7 covers Modularizing Rules with Interface Methods. Lecture 8 covers Performance Tuning using Rule Composition.
 
Lectures 9 - 10
Lecture 9 covers more on Module Interfaces. Lecture 10 covers Multiple Clock Domains.
 
Lectures 11 - 12
Lecture 11 covers Compiling, Running and Debugging. Lecture 12 is a summary Conclusion to the training.
 
 


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