As market demand drives the need to pack more performance and functionality at ever-smaller geometries,
designers begin to hit a wall of complexity—especially as we enter the nanometer era. Cadence is the world's largest supplier of EDA technologies and engineering services.
We help meet their challenges by providing a new generation of design solutions that speed advanced IC designs to volume.
Richard Goering interviews Cadence's Mike McNamara
Mike ("Mac") MacNamara, general manager of the Systems Software group at Cadence Design Systems, discusses high-level synthesis (HLS) and its capabilities. Mac defines HLS; explains who's using it and why, and discusses how HLS improves functional verification and the quality of RTL code. He concludes with a look at Cadence's strategy in the electronic system level (ESL) design marketplace.
The industry's first complete solution integrates logic design, verification,
and implementation technology—all enabled with the Si2 Common Power Format (CPF)—to improve
productivity, reduce risk, and achieve optimal trade-offs among timing, power, and area.
Accurate prediction of silicon performance, power, and yield in sub-65nm designs demands a holistic 360-degree analysis solution, not isolated point tools. Designers must now consider advanced variability concerns such as statistical analysis, and new additive requirements for critical area analysis (CAA), thermal effects, lithography, chemical-mechanical polishing, and overall design for yield (DFY). Signoff for manufacturability with Encounter Timing System combines the interdependencies of logical, physical, electrical, and manufacturing analysis in a single, comprehensive view for final optimization and signoff. It also offers a debug environment for timing, SI, power, and clock trees to quickly and easily perform root-cause analysis, enabling faster time to market.
This demo focuses on the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment.
You will discover some of the new features and functionality that are available, focusing on the enhanced productivity that
designers enjoy with the introduction of assistance. You will also learn about the constraint management system that can be
used to pass information the schematic through to layout.
Discover the new, common cockpit that integrates all the Virtuoso products designers can access at any point and time during the design. You will see how to quickly perform area estimation on a piece of data, obtain the information, and plug it into a floor planning technology. You will also see simple editing to correct violations, the use of pin placement technology, and design optimization.
Explore how constraints can help designers manage their design environment. The demo will take you from design schematic into layout, and then into routing all in one, easy-to-use design cockpit.
High-performance Custom Routing and DFM Optimization for Advanced Process Nodes using the Cadence® Space-based Router and Chip Optimizer Category: Back End - Physical Design,
Design for Manufacturing
View the all new innovative space-based gridless analysis driven routing and yield optimization solutions from Cadence Design Systems. The Cadence Space-based Router and Cadence Chip Optimizer deliver a silicon proven full-chip routing and DFM optimization solution that provide concurrent design and manufacturing convergence for improved design performance, manufacturability and yield at 65nm and below processes. The demo features the Cadence Space-based Router which is a custom IC high capacity, high performance convergent design routing solution for custom digital and analog mixed signal designs. The demo also features the Cadence Chip Optimizer, which is complimentary to the Cadence Space-based Router or any IC design routing solution for post-route model driven manufacturing and yield optimization. Together the two products deliver an award winning routing and optimization solutions for today and tomorrow's advanced process node requirements.
Discover how you can effectively design mixed-signal chips, regardless of
design size. Virtuoso AMS Designer is the latest technological break through that
brings the power of behavioral modeling to the IC designer. It tackles the difficult
challenge of converging massive digital designs with precise analog circuitry and
simulating them accurately and quickly, while using Verilog-AMS/VHDL-AMS languages,
Virtuoso Schematic Editor schematics, Assura extracted views, timing views from SoC Encounter,
and textual descriptions for NC-Sim. (This demo features custom design products from IC 5.1.41 release).
Solving New Challenges in Nanometer Design with Assura Physical Verification Category: Back End - Extraction,
Physical Verification
In nanometer design, physical verification including layout parasitic
extraction is a must to achieve manufacturing sign-off. This demo features the use of
Assura RCX, the industrys standard for 3D device-level parasitics extraction, to
accurately extract and optimize the on-chip parasitics of a VCO block generating an
Extracted View with parasitics for subsequent simulation of a digital/mixed-sign design.
An overview of the Assura DRC, LVS for nanometer designs will also be presented.
(This demo features a previous release of Assura physical verification).
You can not improve what you can not measure. Learn how to implement a metric driven verification environment to improve predictability, productivity, and quality of your chip development.
Cadence C-to-Silicon Compiler (CtoS) is next-generation high-level synthesis technology for automating SoC IP development and reuse. Using embedded logic synthesis, CtoS automatically generates synthesizable RTL and/or technology-mapped gates for both datapath and control functions, starting from timed and untimed C/C++/SystemC(r) algorithm descriptions. Using CtoS, designers can reduce engineering effort by up to 90%, while achieving quality of results at or above whatever is possible using best manual RTL coding practices.
This demonstration highlights the new SoC Functional Verification Kit and how functional verification methodologies go beyond basic tools: it allows team members lacking verification expertise to begin verification much earlier and work as though they were verification experts. These methodologies are displayed and comprehended with a new interactive GUI driven navigator, allowing virtually anyone to quickly grasp and understand verification flows, such as designer flows, HW/SW co-verification flows, low power and bus compliance management flows. Attendees will learn how these new methodologies can improve productivity, reduce risk, and increase quality.
Verifying protocol compliance is typically time consuming and requires extensive protocol expertise. This demo shows off Cadence's new Compliance Management System (CMS) that automates compliance verification. With CMS, you can reach 70+% functional coverage without writing a single test. We’ll show you how easy it is to apply CMS to your AMBA or PCI Express verification project and briefly overview Cadence's extensive Verification IP portfolio.
Improve verification productivity with formal-assertion verification that provides easy adoption,
ease-of-use, and broad assertion support including SystemVerilog assertions, PSL, OVL, and the Incisive Assertion Library.
Allegro PCB SI, an integrated design and analysis environment, tackles the problems found in today's high speed systems. See how to design and verify high speed serial links, high speed memory interfaces, and power delivery networks.
This demo will show Cadence's Constraint-Driven HDI design flow in Allegro PCB Editor. The Constraint-Driven flow integrates HDI rules with proven constraint-driven flow for electrical constraints. It will also show automation provided to create HDI designs that are correct-by-construction.
This demo will show how Allegro Constraint Driven PCB design flow allows engineers to embed constraints within their design and enable a constraint driven PCB layout flow to avoid unnecessary physical prototype iterations.
This demo introduces Cadence's unique solution for FPGA-PCB Co-design to accelerate time to integrate large pin count, complex FPGAs in production ready PCB Design flow. It will show how FPGA designers can quickly generate placement-aware pin assignment of one or more FPGAs on a PCB, achieve better FPGA performance through optimum utilization of FPGA resources.
Implementing RF circuits on PCBs Category: PCB Design
On today's designs, it is more likely than ever that mixed technologies such as analog, digital, and RF share the same PCB. Dealing with this mixture of technologies and specific RF requirements poses unique challenges for PCB designers and CAD tools. Cadence® Allegro® PCB RF option provides an RF-aware design capabilities including intelligent layout for parametrically creating and editing RF geometries, a flexible shape editor, and data-aware bi-directional IFF interfaces. Through bi-directional interfaces, RF circuits can be simulated and validated for signal quality and performance. The entire set of functionalities is vital to the successful physical design and implementation of RF circuits.
Global Route Environment technology for Cadence® Allegro® PCB design Category: PCB/MC
Discover a new route to advanced PCB design and layout and learn how using intelligent automation can eliminate manual processes while preserving the designer's intent. This demo will highlight the new Global Route Environment technology for Cadence® Allegro® PCB design. The Global Route Environment technology combines a graphical interconnect flow planning architecture and a hierarchically-aware global routing engine to provide PCB designers with an automated, intelligent planning and routing environment. This demo will highlight the new use model paradigm and how it solves ultra-complex PCB interconnect challenges where strategic planning and interconnect routing could previously only be done by manual methods.
