 |
|
 |
|
 |
| Category:
Front End - FV-HW/SW CoDesign/Verification |
|
|
|
|
|
C-based design and synthesis from ANSI-C algorithms to optimized FPGA gates. The tools simulates cycle-accurate C models, co-simulates with RTL and Matlab,
and synthesizes the Handel-C implementation language to RTL models, and gate-level EDIF netlists for FPGA. The tool is used for algorithm acceleration in FPGA,
and rapid implementation to FPGA for production or SoC prototyping.
This on-line demo walks through a design example from specification to FPGA implementation showing the Software-Compiled System Design
methodology. The demo provides a detailed review of the Celoxica DK Design Suite environment
as applied to the development of an image processing system based on a JPEG2000 algorithm. |
| |
| |
|
|
|
|
|
