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Targeted ROI is critical in today's electronic designs: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market. Jasper delivers industry-leading EDA solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. The broad spectrum of formal technology applications includes architectural analysis, RTL development with early debug, verification, silicon debug, and design and IP leverage. Jasper customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. |
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Kathryn Kranen, CEO of Jasper Design Auomation, discusses formal verification as a broad spectrum of applications including architectural analysis, RTL design and debug, verification, and silicon debug. Kathryn also addresses the key questions of: Where, When and How can formal be used most effectively?
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Functional Verification: Formal Tools |
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Flagship JasperGold™ unleashes formal verification on top project challenges spanning the IC development cycle. JasperGold leads the industry in proof power, with patented engines and abstractions for capacity and performance; advanced Visualize™ technology, and new ProofGrid™ for deployment.
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Flagship JasperGold™ unleashes formal verification on top project challenges spanning the IC development cycle. JasperGold leads the industry in proof power, with patented engines and abstractions for capacity and performance; advanced Visualize™ technology, and new ProofGrid™ for deployment.
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| Category:
Functional Verification: Formal Tools |
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Active Design™ accelerates design creation and IP leverage with system and databases for RTL analysis. Powered by Behavioral Indexing™ and Visualize™ technology, it promotes RTL design development, quality and reuse.
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New Active Design™ delivers an analysis system and databases for design development and reuse. Powered by Behavioral Indexing™ and Visualize™ technology, it accelerates design and IP creation and leverage.
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Managers who are responsible for both chip design and verification at the project level understand that it makes extreme economic sense to kick-start the verification process as early in the design flow as possible. But this is sometimes easier said than done. For some insight into how Jasper can help, look here. |
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