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In this interview, Rajeev announces "Titan", his new Virtuoso-killer, along with discussing Pcells, Ciranova, PDKs, Analog Artist, Talus, Mojave, QuickCap, Quartz-TLX, OA, MatLab, process migration, Sagantec, "AnalogWare", Cosmos, Pulsic, fabs, 65 nm, 45 nm, the Synopsys-Magma lawsuit, Jay Vleeschhouwer, bean counters, Cadence, and Mentor Calibre. |
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Design For Test/ATPG |
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The increased complexity and smaller feature sizes of today's chip designs make it more complicated to test manufactured ICs. Traditional test approaches lack the performance, accuracy and capacity to deliver the required level of test quality and turnaround time for nanometer ICs. View this demo to learn how Magma's advanced Talus® ATPG and Talus ATPGX software allows designers to improve test quality and turnaround time.
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2/27/2008 - Magma Magma Introduces Titan – First Platform to Combine Full-Chip, Mixed-Signal, Analysis and Verification for IC Design | 2/27/2008 - Magma Magma Acquires Sabio Labs, Enhances Titan Mixed-Signal Design Platform | 2/27/2008 - Magma Magma Titan Platform Supports IPL Standards and Ciranova PyCell Libraries for Next-Generation Analog/Mixed-Signal Design | 2/27/2008 - Magma Magma Launches QuickCap TLx, a new Interconnect and Transistor Extractor |
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Mixed-signal chip finishing is often performed by hand, and it includes a number of tasks that occur right before the chip tapeout. Because of the lack of automation, chip-finishing activities and actions often fail to be reflected back into the main design, which can lead to major issues for their reusability in future generations of the design. Magma has responded by introducing a truly unified, automated, full-chip mixed-signal design, analysis, and verification solution called Titan. The unprecedented level of integration and automation provided by Titan enables significant jumps in productivity in the areas of chip finishing, analog/custom digital design implementation and full-chip circuit simulation. For more information, download the white paper.
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