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Synplicity® solutions enable the rapid design of FPGAs, PLDs and CPLDs and are used in a wide range
of communications,
military/aerospace, consumer, semiconductor, computer, and other electronic systems markets. |
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Category:
Front End - FV-Emulation
This whiteboard demonstrates the revolutionary new TotalRecall technology which enables you to debug and verify ASIC/SOC designs, ASSPs, and FPGAs at real hardware speed with full signal and state visibility. |
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Category:
Front End - Design Synthesis;
Back End - Physical Synthesis
In this whiteboard discussion, Ken McElvain, Synplicity's founder and CTO, discusses the evolution of modern FPGAs to
their present 65 nanometer form and what the implications are for the design of FPGAs in the future. |
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Category: Front End - ESL/Architectual Design,
Design Synthesis
This whiteboard discussion introduces the concept of True DSP synthesis and how it is different from other methods of
going from DSP algorithm to RTL code for hardware implementation. This discussion covers
topics including design languages, the importance of a technology-independent flow, and
automatic application of DSP
synthesis optimizations. |
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Here's an interview I recently did with Ken McElvain on his transition from HP lackey to
Mentor R&D guy to Synplicity founder. We discussed being an Air Force brat, HP, IBM, Silicon Compilers, Autologics & Autologics II, leaving Mentor,
starting Synplicity, Xilinx troubles, free vs. buy, Altera, Quicklogic, Synopsys, their IPO, his wife, CEO Gary, the Internet bubble, Structured ASICs,
LSI Logic, FPGA physical synthesis, and his new unannounced "Total Recall" product.
Enjoy! - John |
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Category:
Front End - Acceleration
HAPS is a modular board system that provides real-time speed, real-time debugging and full ASIC functionality for ASIC prototype designers. The system is composed of stackable multi-FPGA mother boards and one or more standard or custom-made daughter boards. Using HAPS, the ASIC prototype gives designers the same functionality and performance as the ASIC. This presentation describes the HAPS-50-series of mother boards in detail. |
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Category:
Back End - Physical Synthesis, FPGA Tools
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This video provides an overview of Synplicitys patented graph-based physical synthesis technology and introduces
Synplify Premier software, the ultimate FPGA design and debug solution. |
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Category:
Front End-Design Synthesis,
Back End Physical Design,
Back End Physical Synthesis
The Synplify DSP solution accepts algorithmic specifications from such tools as MATLAB®/Simulink®,
and automatically generates high-quality, optimized RTL for hardware implementation. |
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Category:
Front End-Design Synthesis,
FPGA Tools
Explore the Synplify Pro® solution, the fast and efficient FPGA
synthesis tool which can be applied to a variety of target devices. The video demonstrates
success in meeting both timing and area specifications. |
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Category:
Front End - FV-Debug Tools
The Identify tool is the only software that allows FPGA and ASIC prototyping designers to functionally debug
their hardware directly in their RTL source code. In this demonstartion, you will see how Identify software
reduces your hardware debug time by providing an easy and fast RTL-based debug environment. For FPGA design
or ASIC prototyping, Identify software provides the quickest way to find bugs in your hardware. |
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