ARM / SYNOPSYS: Accelerate AMBA 3 AXI Design Verification with DesignWare In these four in-depth videos, ARM and Synopsys show how Synopsys DesignWare® verification IP allows you to rapidly validate your AMBA® 3 AXI™ protocol-based designs. The Synopsys DesignWare solution reduces risk by increasing functional coverage and ensures successful and rapid time-to-market. Design starts are ramping up for AMBA 3 AXI and it’s looking like the next de facto standard high speed bus architecture.         AMBA 3 AXI The Protocol Advantage David Ptak, Synopsys Today’s technical and market pressures drove the creation of the AMBA® 3 AXI™ protocol, which is designed to enable implementation of a high performance scalable bus interconnect architecture. This session begins with a short intro to the AMBA 3 AXI protocol followed by a deep technical session explaining the protocol itself and how it enables high-performance, high-bandwidth, low-latency bus interconnect operation. The presentation leverages the DesignWare Verification IP to introduce the protocol and provides insight into jump starting your own AMBA 3 AXI design verification tasks.   Hardware Platform-Based Design Using ARM PrimeCell Technology Ben Cade, ARM This presentation discusses the steps involved in hardware platform creation. Beginning at the product requirements capture phase, identified are key functional components and mapping these to both internal and external IP. The work flow from IP selection through configuration and optimization to final implementation ready delivery is covered and uses a variety of ARM® processors and PrimeCell® IP to demonstrate how to take full advantage of both the methodology and the AMBA® protocol.   Synopsys/ARM Verification Methodology Ramnath N. Rao, Synopsys The Verification Methodology Manual (VMM) for SystemVerilog is an open verification methodology and library based on Synopsys’ proven Reference Verification Methodology. This session provides insight into the VMM methodology and how it helps maximize design quality, promote reuse among components, and emphasizes a layered, coverage driven, constrained random verification environment. The session documents the layered architecture, verification flow and transaction channel objects as defined by the Verification Methodology Manual for SystemVerilog.   DesignWare VIP Detailed Usage Darrin Mossor, Synopsys The Synopsys DesignWare Verification IP for AMBA 3 AXI provides an effective method of verifying AMBA 3 AXI protocol based designs. This session provides in-depth technical insight into working with the Verification Methodology Manual for SystemVerilog compliant and “AMBA 3 Assured” DesignWare Verification IP. The DesignWare Verification IP for AMBA 3 AXI includes master, slave, monitor and verification interconnect components with each supporting all the AMBA 3 AXI address, data widths, and protocol transfer and response types. The session documents how this full featured command set can be utilized to create both a directed test transaction environment as well as how to leverage the coverage driven, constrained random verification interface support.     OTHER TRAINING VIDEOS • Bluespec SystemVerilog • SystemVerilog Assertions Tutorial • Transition to SystemVerilog for Verification Tutorial More training >>
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