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Interest in the use of SystemVerilog for verification is strong. Not surprisingly, many organizations that have lead the evolution in verification by using the proprietary HVL e,
are exploring a move to standards and SystemVerilog. SystemVerilog is the recently ratified hardware description and verification language (HDVL) standard—a major
extension of the established IEEE 1364-2001 Verilog language. This seminar provides guidance on transitioning to SystemVerilog for verification by showing and contrasting
language capabilities and how common verification structures and techniques are implemented in both languages. This seminar will be particularly valuable to those using
Verisity®’s e language.
Learn practical and up-to-date guidance on transitioning to a standards-based verification methodology built on SystemVerilog.
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