This seminar reviews advanced verification topics for complex SoC designs and how to use SystemVerilog to
apply them in practical ways.
Part I Part II Part III Part IV
Introduction Adopting Methodology Components Tying It Together Implementing a Methodology
with Questa
The first half of the seminar reviews testbench automation; constrained-random verification; assertions; functional coverage;
formal verification.

The seminar continues with a discussion of these topics to show what they can (and can't) contribute to a verification methodology,
and what value the Questa verification platform provides for such a methodology and shows how to architect and assemble a
testbench to deploy these techniques.
  Other Mentor Graphics' seminars and demos >>  
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