Jasper Presenting "New Technologies In Formal Verification" at SAME 2010 Forum October 7
Mountain View, Calif., 07/28/10 –

Jasper Crosses the Design-to-Verification Chasm
Mountain View, Calif., 06/02/10 – New Data-Sharing Capabilities in ActiveDesign and JasperGold Unify Design and Verification Teams

See Jasper Formal Verification in Action at DAC June 13-18, Booth 1337
Mountain View, Calif., 05/18/10 –

Jasper's Kathryn Kranen Re-Elected As EDAC Vice Chair
Mountain View, Calif., 04/20/10 –

Industry's first HDMI 1.4 Transceiver for consumer audio/video designs delivers ultra-fast switching technology, while reducing design complexity and cost
Norwood, MA, 09/29/09 – - Single-chip ADV7623 HDMI 1.4 transceiver with ADI's Xpressview™ switching technology enables designers to bring rich feature sets to home and professional AV systems.

Cadence Extends Performance Leadership with Expanded Multi-Core Support
SAN JOSE, Calif., 09/29/09 – Enhanced Engine Performance in Design, Verification, Custom, PCB and IC Packaging Broadens Cadence Multi-Core Support

Cadence Physical Verification System Supports TSMC's Interoperable iDRC and iLVS Formats for 40-Nanometer Design
SAN JOSE, Calif., 09/29/09 – Cadence Physical Verification System Delivers Performance and Integration for High-End SoC Designs Implemented in Advanced TSMC Processes

Jasper Names HASS Technology Distributor for China
Mountain View, Calif., 09/01/09 – Jasper Design Automation, provider of advanced formal technology solutions, has named HASS Technology as its distributor in China and Taiwan.

Tilera Adopts Broad Range of Cadence Solutions for Multicore Processor Design
SAN JOSE, Calif., 08/25/09 – Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that fabless semiconductor company Tilera Corporation has utilized the full range of Cadence design technologies to develop its innovative, highly scalable multicore embedded processors.

Siemens Adopts CoWare Electronic System Virtualization Solutions For the Development of Industrial Ethernet Components
SAN JOSE, Calif., 08/17/09 – CoWare Technology and Deployment Services Expertise Used for Optimized System Architecture and Accelerated Software Development

Nethra Enlists Cadence Incisive Palladium Accelerator/Emulator To Speed Development of Advanced HD Image Processor
SAN JOSE, Calif., 08/03/09 – Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Nethra Imaging, Inc. reduced the development time of a high-definition (HD) image processor design using the Cadence® Incisive® Palladium® II Accelerator/Emulator.

Jasper Design Automation Introduces Multi-Proof JasperCore For Powerful, Scalable Formal Verification Deployment
Mountain View, Calif., 07/13/09 –

Jasper Design Automation, provider of advanced formal technology solutions, announces its latest product, JasperCore™. JasperCore harnesses the proven capabilities of the company's formal analysis engines to boost productivity and decrease the cost of deployment by performing numerous parallel runs using ProofGrid™, a new capability that distributes formal technology. Together, JasperCore and ProofGrid allow users to implement multiple proofs, tasks, and applications, across multiple cores and computers, efficiently serving multiple users, even across multiple business units.

CoWare Reduces Design Cost for Complex ARM AMBA Platform Optimization
SAN JOSE, Calif., 06/15/09 – New Interconnect and Memory Subsystem Performance Optimization Design Flow Leverages Years of Production Use Experience

ARM Selects Jasper for Formal Verification of IP
MOUNTAIN VIEW, Calif., 05/19/09 – Jasper Design Automation, provider of advanced formal technology solutions, today announced its JasperGold® Verification System has been adopted by ARM.

Cadence Kicks Off Worldwide User Conferences with CDNLive! EMEA 2009
MUNICH, Germany, 04/30/09 – Cadence Technology Users to Learn and Exchange the Latest Electronic Design Ideas


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