These demos present an in-depth view of various back end design products relative to post layout analysis. Scroll down to view all demos or select a vendor name from either menu.
Incentia Optimal Sequence
Incentia TimeBench Environment
TimeCraft is the fastest gate-level full-chip static timing analyzer in market today. It contains industry leading features for nanometer designs, including location-based on-chip-variation, parallel multi-mode multi-corner timing analysis, and signal integrity analysis for crosstalk and noise.

Signal Integrity Design Assistants
SIDEA™ (Signal Integrity Design Assistants) is a complete suite of signal integrity design assistants for parasitic extraction and S-parameter conversion, manipulation and modeling. SIDEA was developed to put most-often used signal integrity design tools in one place so engineers need not mix and match software from various sources.

COOLTIME™ - Like, Instantaneous, Dude
The "way cool" tool to see this year is CoolTime, providing electrical integrity analysis for the concurrent analysis of power, voltage drop, timing, and signal integrity. With an emphasis on instantaneous voltage drop, it overcomes limitations of existing static IR-drop tools.

PHYSICALSTUDIO™ - Concurrent Design Closure
Proven in more than 100 tapeouts at feature sizes down to 90 nanometers, the concurrent analysis-based optimization of timing, SI, voltage drop, and leakage power provided by PhysicalStudio continues to win converts with leading designers worldwide.

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