These demos present an in-depth view of various intellectual property products relative to development tools. Scroll down to view all demos or select a vendor name from either menu.
ARC Cadence Interra Systems Mosaid - Virtual Silicon Z Circuit Automation
Developing the lowest power MP3 solution for SoCs
This video demonstrates the power and ease of ARC's highly regarded ARChitect IP Configurator tool. In just 40 minutes, James Campbell, Field Applications Engineer for ARC, provides an "engineer to engineer" tutorial on the four stages to developing an extremely low power MP3 solution. Along the way, Mr. Campbell demonstrates many of the accompanying tools required to complete the design including cycle accurate simulation, software modeling, codec development, functional simulation, RTOS configuration, compilation, debugging and FPGA prototyping.

Performing mixed-signal design layout with Virtuoso Accelerated Layout
Discover the power of Virtuoso Layout Editor Turbo and Virtuoso XL Layout Editor, both part of the accelerated layout suite of the Virtuoso custom design platform. Learn how they help automate and accelerate your most complex custom physical layout design. This demo will take you through generating Pcells, the utilization of Qcells, as well as building an environment and using Qcells all the way up into Virtuoso XL Layout Editor. The demo also features design rule-driven, guard ring, and wire editor functionalities. (This demo features custom design products from IC 5.1.41 release).

Interra Memory Development System
This in-depth demo shows how MC2 automates the design process for standard and embedded memories while also providing a platform for migration to new processes. MC2 enhances the overall methodology for the design and distribution of memories to ensure the reuse of a base design over many generations of sub-micron processes.

The Power Leakage Issue in SoC Design
In this whiteboard session, Dan Hillman, a Silicon Valley veteran, reviews the sources of dynamic and static leakage and power consumption in SoC designs at 130 and 90 nanometers and compares gate bias and back bias as solutions for the reduction of leakage current.

Z Circuit Library Analyzer
The Z Circuit Library Analyzer is a tool targeted towards library integration engineers to help them with library tracking and analysis. It is the first library analysis system that that gives you a thorough understanding of your choices so that you can make the right decisions.

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