These demos present an in-depth view of SoC Development tools relative to Low Power.
Developing the lowest power MP3 solution for SoCs
This video demonstrates the power and ease of ARC's highly regarded ARChitect IP Configurator tool. In just 40 minutes, James Campbell, Field Applications Engineer for ARC, provides an "engineer to engineer" tutorial on the four stages to developing an extremely low power MP3 solution. Along the way, Mr. Campbell demonstrates many of the accompanying tools required to complete the design including cycle accurate simulation, software modeling, codec development, functional simulation, RTOS configuration, compilation, debugging and FPGA prototyping.

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