Aldec delivers industry-proven mixed HDL verification products and services to FPGA and ASIC designers.
Active-HDL: A complete FPGA Design Entry and Verification Environment
Category: Front End: Behavioral Simulation, Design Entry, FV-Simulation,
FV-HW/SW Codesign/Verification
Booth Visit
Active-HDL is the leading design entry and simulation environment for all FPGA and CPLD device families. It provides the flexibility and advanced features to support today's most complex designs for VHDL, Verilog, C/C++ and EDIF simulation from a single design entry and verification environment.
7/19/2006 - Aldec
Aldec Extends Code Coverage Analysis Offering
7/10/2006 - Aldec
Aldec and Synplicity Partner on Encrypted IP Flow
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