ChipVision supplies low power analysis, estimation and optimization solutions SoCs. ChipVisionā€™s ORINOCO is the only design tool that bridges the ESL, at which the most significant reduction of power consumption can be achieved, to low power implementation at the RT Level. Target application areas are power-sensitive electronic devices in the wireless and multimedia domain.
ChipVision ORINOCO® - From Algorithm to Low-power Implementation
Category: Front End - ESL/Architectural Design, Behavioral Simulation, FV-Design Analysis,
Design Planning-Floor Planning
Booth Visit
This in-depth demo shows how ORINOCO enables you to define the low-power optimized micro architecture for data-flow dominated blocks in SoCs. Starting from an algorithm defined in C or SystemC ORINOCO DALE optimizes the micro architecture of a block for implementation and guides your optimization of the number of algorithmic resources, memory accesses and allocations, resulting in the best low-power architecture.
5/14/2007 - ChipVision
ChipVision breakthrough ESL technology enables interactive creation of RTL code optimized for low-power consumption
6/1/2005 - ChipVision
ChipVision delivers industry first Leakage Power estimation technology at the ESL
3/7/2005 - ChipVision
ChipVision Design Systems AG joined the Open SystemC Initiative (OSCI)
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