ABOUT SEQUENCE DESIGN
Sequence Design provides tools for analysis and optimization of power and
timing and signal-integrity, based on interconnect modeling technology, for
designers working at 130-nm and below.
Attack the challenges of low power design
holistically, from RTL to GDS. Manage and reduce power. Avoid power problems.
The only comprehensive tool suite, with advantages for managers, for SoC
architects and designers, and for the physical implementation team: Design for
Power with Sequence.
Vic Kulkarni CEO
Vic describes how Sequence helps engineers overcome the difficult challenge of
converging massive digital designs with precise analog circuitry and simulating
them accurately and quickly while using Verilog-AMS/VHDL-AMS languages,
Schematic Editor schematics, Assura™ extracted views, timing views from SoC
Encounter, and textual descriptions for NC-Sim.