Sequence Design provides tools for analysis and optimization of power and timing and signal-integrity, based on interconnect modeling technology, for designers working at 130-nm and below.

Category: Front End - Timing and Power Analysis; Low Power - Front End, Back End

  Attack the challenges of low power design holistically, from RTL to GDS. Manage and reduce power. Avoid power problems. The only comprehensive tool suite, with advantages for managers, for SoC architects and designers, and for the physical implementation team: Design for Power with Sequence.

Vic Kulkarni CEO
Vic describes how Sequence helps engineers overcome the difficult challenge of converging massive digital designs with precise analog circuitry and simulating them accurately and quickly while using Verilog-AMS/VHDL-AMS languages, Schematic Editor schematics, Assuraâ„¢ extracted views, timing views from SoC Encounter, and textual descriptions for NC-Sim.

10/3/2007 - Sequence
S3 / Via Accelerates Design Closure 30% With Sequence CoolProducts
7/17/2007 - Sequence
Sequence and Faraday Collaborate on Integrated Low Power Design Flow
7/10/2007 - Sequence
Sequence CoolProducts Chosen By Tektronix For Power Signoff
6/4/2007 - Sequence
STARC Adding Sequence Power-Gating Analysis To Advanced Design Flow

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