Verplex Video Channel



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	Streaming Videos

			Verification Solutions for SoC C. Michael Chang, President and CEO, explains how Verplex is delivering the highest speed, highest capacity and most user-friendly RTL verification and equivalence checking solutions for large, multi-million gate designs.



			Customer Application - Philips Semiconductor Senior Designer Ralph Escherich explains how Verplex's Tuxedo-LEC solution for equivalence checking provides Philips with the necessary robust functionality for its increasingly larger and more complex SoC designs.





	Recorded Format Videos We’ll mail the following programs at no cost on Video CD. To select a video, use the “Add to basket” button. Add as many as you like, then select "Checkout."

Technology View

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Whiteboard & Demo
C. Michael Chang illustrates how Verplex combines state-of-the-art search technologies with leading-edge abstraction algorithms, and employs an open-source Verilog-based verification library that operates seamlessly with simulation. Next, Dino Caporossi, VP Marketing, provides an in-depth demo, showing how Verplex solutions are used by ASIC and IC designers to identify embedded bugs early, to ensure no errors are introduced during design iteration and revision, and to compare designs at different levels of abstraction.

Integrated Solutions for SoC Design

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BlackTie™ Functional Checker
Kuang-Chien Chen, VP R&D, explains how SoC designers use BlackTie, Verplex's high capacity RTL formal design verification tool, to identify and resolve embedded bugs early in the design process, resulting in significant time and cost savings.

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Tuxedo™ LEC
Dino Caporossi reviews the advantages of the Tuxedo LEC equivalence checking solution, including its exceptional debugging capability, its easy integration into SoC designs, and its fast verification speed for the largest multi-million gate designs.

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Tuxedo™ LTX
Dino Caporossi discusses Tuxedo LTX, a groundbreaking tool that addresses a critical market need - the ability to accept a switch-level Verilog or SPICE transistor netlist as input, and automatically extract a higher level Verilog description from it.