The leader in formal and functional verification,
Verplex products are rated #1 in speed, capacity and usability.

When it comes to verifying correct functionality, achieving design closure is more and more challenging for system-on-a-chip (SOC) design. A recent independent study showed that more than half of all chips require one or more re-spins, and that functional errors were found in 74% of these re-spins.

Functional closure is achieved when an implemented design meets its specification. A thoroughly verified Register Transfer Level (RTL) design, or golden RTL, undergoes massive transformations and iterations before the final layout, and each step in this process can introduce logical inconsistencies, or bugs. Equivalence checking is a proven "must have" for finding these bugs, but any bugs that are present in the golden RTL reference design may go undetected to silicon. Thus, a formal verification methodology employing just equivalence checking is only half of the solution.

Verplex is the market leader in formal verification, offering the only complete solution for functional closure. Verplex's BlackTie™ functional checker eliminates structural and semantic inconsistencies in the RTL reference design, thereby ensuring your RTL is golden prior to implementation. BlackTie is tightly integrated with Conformal™ Logic Equivalence Checker (LEC) and Transformal™ Logic Transistor eXtractor (LTX) to ensure your golden design is correctly implemented from RTL to layout. Using Verplex, you will "Design it golden and keep it golden.™"

Verplex Systems, Inc., 300 Montague Expressway, Suite 100, Milpitas, CA 95035
Phone: 408-586-0300 Fax: 408-586-0230